Kuo-Ning Chiang (江國寧)

Chair Professor (講座教授)

IEEE Fellow, ASME Fellow, STAM Fellow, iMAPS Fellow

       Academician (院士), Russian International Academy of Engineering (IAE)

Advanced Microsystem Packaging & Nano-Mechanics Research Lab.

Advanced Microsystem Packaging and Nano-Mechanics Research Lab.
Department of Power Mechanical Engineering, National Tsing Hua University
No. 101, Sec. 2, KungFu Rd.
HsinChu 300, Taiwan
E-mail: knchiang@pme.nthu.edu.tw
Tel: 886-3-574-2925
FAX: 886-3-574-5377

 

 Vita:

      Professor K. N. Chiang received his Ph.D. degree from the Georgia Institute of Technology, USA. Currently, he is the Chair Professor of the National Tsing Hua University in Hsinchu, Taiwan. From 2010 to 2013, he served as General Director of the National High-Performance Computing Center, which is the National Strategic Research Center of Taiwan. He has received three times outstanding research award from the Ministry of Science and Technology of Taiwan and has published more than 300 technical papers in international journals and conference proceedings. He has awarded more than 50 invention patents. Currently, he is Editor-in-Chief of the Journal of Mechanics (SCI), Senior Area Editor of the IEEE Transactions on Component, Packaging and Manufacturing Technology (SCI), and he was the Associate Editor of the 4 SCI Journal and the board member of IEEE-EPS.

 

      He has made great achievements in simulation-based science and technology. He successfully combined simulation design with artificial intelligence technology and applied it effectively to semiconductor-related designs. His technology has greatly reduced product development time and development costs. He is a world-renowned scholar in above research and application fields. He has worked with many major electronic packaging, semiconductor and LED companies such as ACET, TSMC, UMC, EPISTAR (LED), VIA, etc.

 

       Currently, Professor Chiang is the Chairman of Society of Theoretical and Applied Mechanics, Taiwan. He is the IEEE / ASME / STAM / iMAPS Fellow and the Academician of Russian International Academy of Engineering (IAE).

 

Research Area:

     Advanced Microsystem Packaging, MEMS/NEMS Design, Nano-Mechanics and Nano-Structure Analysis, Artificial Intelligence Methods, Computational Solid Mechanics, Nonlinear Finite Element Method and Contact/Crash Analysis.

   

Education:

·     Ph.D., ME of Georgia Institute of Technology

·     M.S., ME of University of South Carolina       

·     B.S. National Cheng Kung University

        

 

Career:

n   Present:  Chair Professor, National Tsing Hua University

n   Present:  Editor-in-Chief, Journal of Mechanics (SCI)

n   Present:  Senior Area Editor, IEEE Transactions on Components, Packaging, and Manufacturing Technology (SCI)

n   Present:  Director, Advanced Packaging Research Center, NTHU

n   Present:  Adjunct Chair professor, Feng Chia University

n   Present:  Research Fellow, Microsystem center of ITR

n   Academician, Russian International Academy of Engineering

n   ASME Fellow

n   STAM Fellow

n   IEEE Fellow

n   iMAPS Fellow

n   IEEE-CPMT Board of Governors

n   Award committee, IEEE-CPMT

n   Convener, Solid Mechanics Research Program, Ministry of Science and Technology

n   Vice President, Asia Liaison Committee of International Microelectronics and Packaging Society (ALC, IMAPS)

n   Director of National Center for High-Performance Computing

n   Chairman of IMAPS - Taiwan (2006-2012, International Microelectronics and Packaging Society)

n   Co-Editor-in-Chief, IEEE Transactions on Components, Packaging, and Manufacturing Technology

n   Associate Editor, IEEE Transactions on Advanced Packaging

n   Associate Editor, Journal of electronic package ASME Transactions

n   Associate Editor, Journal of Mechanics

n   Associate Editor, IEEE Transactions on Components and Packaging Technologies

n   Engineering Director of ERSO/ITRI (2003-2005)

n   Secretary-General of ASME Taiwan Section (2002-2005)

n   Chairman of Key Application Committee – ERSO/ITRI (2005)

n   Director of R&D Division, NCHC (1993-1998)

n   Board Member of IMAP (International Microelectronics and Packaging Society) - Taiwan

n   Board member of KingPak Technology Inc.

n   Board member of Argosy Research Inc.

 

 

Journal Papers

  • Q. H. Su and K. N. Chaing, "Predicting Wafer-Level Package Reliability Life Using Mixed Supervised and Unsupervised Machine Learning Algorithms", Materials, Vol.15, pp.3897-3911; https://doi.org/10.3390/ma15113897,
  • Y. W. Huang and K. N. Chiang, "Study of Shear  Locking Effect on 3D Solder Joint Reliability Analysis" Journal of Mechanics, Volume 38, 2022, Pages 176–184, DOI10.1093/jom/ufac012, April 29 2022.
  • S. K. Panigrahy, Y. C. Tseng, B. R. Lai, and K. N. Chiang, "An Overview of AI-Assisted Design-on-Simulation Technology for Reliability Life Prediction of Advanced Packaging", Materials, 14, 5342, https://doi.org/10.3390/ma14185342, Sept. 2021.
  • P. H. Wang, Y. W. Huang, and K. N. Chiang, "Reliability Evaluation of Fan-out Type 3D Packaging-on-Packaging", Micromachines, 12(3), 295,https://doi.org/10.3390/ma14185342, Mar. 2021
  • P. H. Wang, Y. C. Lee, C. K. Lee, H. H. Chang, and K. N. Chiang, "Solder Joint Reliability Assessment and Pad Size Studies of FO-WLP with Glass Substrate", IEEE Transactions on Device and Materials Reliability, Vol. 21, No. 1, pp. 96-101, DOI: 10.1109/TDMR.2021.3056054, March 2021.
  • H. Y. Hsiao and K. N. Chiang, "AI-Assisted Reliability Life Prediction Model for Wafer-Level Packaging using the Random Forest Method", Journal of Mechanics, Volume 37, pages 28-36, 2021.
  • C. H. Tsai, S. W. Liu and K. N. Chiang, "Warpage analysis of fan-out panel-level packaging using equivalent CTE", DOI 10.1109/TDMR.2019.2956049, IEEE Transactions on Device and Materials Reliability, Volume 20, Issue 1, pp. 51-57, March 2020.
  • C. C. Chang and K. N. Chiang, "Empirical High Cycle Fatigue Assessment Model of MEMS Devices", Journal of Electronic Packaging, Volume 142, 011005-1 to 10, March 2020.
  • C. C. Yang, Y. F. Su, Steven Y. Liang, K. N. Chiang, "Simulation of Wire Bonding Process Using Explicit FEM with ALE Remeshing Technology", Journal of Mechanics, , Volume 36, Issue 1, pp. 47-54, March 2020.
  • Elham Mirkoohi, Daniel E.Sievers, Hamid Garmestani, Kuoning Chiang, Steven Y. Liang, "Three-dimensional semi-elliptical modeling of melt pool geometry considering hatch spacing and time spacing in metal additive manufacturing", Journal of Manufacturing Processes, Vol. 45, Pages 532-543, September 2019.
  • P. H. Chou, S. Y. Liang, K. N. Chiang, "Reliability Assessment of Wafer Level Package Using Artificial Neural Network Regression Model", Journal of Mechanics, Vol. 35, Issue 6, Pages 829-837, 2019.
  • P. L. Wu, P. H. Wang and K. N. Chiang, "Empirical Solutions and Reliability Assessment of Thermal Induced Creep Failure for Wafer Level Packaging", IEEE Transactions on Device and Material Reliability,Volume 19, Issue 1, Pages 126-132, March 2019.
  • L. L. Liao and K. N. Chiang, "Material Shear Strength Assessment of AU/20SN Interconnection for High Temperature Applications", Journal of Mechanics, Volume 35, Issue 1, Pages 81-91, February 2019.
  • V. Ramachandran, K. C. Wu and K. N. Chiang, "Overview Study of Solder Joint Reliability Due to Creep Deformation", Journal of Mechanics,Volume 34, Issue 5, Pages 637-643, October 2018.
  • E. Mirkoohi, J. Q, Ning, P. Bocchini, O. Fergani, K. N. Chiang and S. Y. Liang,"Thermal Modeling of Temperature Distribution in Metal Additive Manufacturing Considering Effects of Build Layers, Latent Heat, and Temperature-Sensitivity of Material Properties", Journal of Manufacturing and Material Processing, Volume 63, Issue. 2, September 2018.
  • C. C. Chang, S.D. Lin and K.N. Chiang, "Development of a High Cycle Fatigue Life Prediction Model for Thin Flim Silicon Structures", Journal of Electronic Packaging, Volume140,Issue 3, September 2018.
  • L. L. Liao and K. N. Chiang, "Nonlinear and Temperture-Dependent Material Properties of AU/SN Alloy for Power Module", Journal of Mechanics, Volume 33 , Issue 5, Pages 663-672, October 2017.
  • V. Ramachandran and K. N. Chiang, “Feasibility Evaluation of Creep Model for Failure Assessment of Solder Joint Reliability of Wafer Level Packaging”, IEEE Transactions on Device and Materials Reliability, Volume PP, Issue 99, Pages 1-1 ,September 2017.
  • C. H. Lee, K. C. Wu and K. N. Chiang, "A Novel Acceleration-Factor Equation for Packaging-Solder Joint Reliability Assessment at Different Thermal Cyclic Loading Rates", Journal of Mechanics, Volume 31, Issue 1, Pages 35-40, February 2017.
  • Y. F. Su, Steven Y. Liang and K. N. Chiang, "Design and Reliability Assessment of Novel 3D-IC Packaging", Journal of Mechanics, Volume 33, Issue 2, Pages 193-203 April 2017.
  • K. C. Wu, and K. N. Chiang, " Characterization on Acceleration-Factor Equation for Packaging-Solder Joint Reliability", Microelectronics Reliability, Volume 65, Pages 167-172, October 2016.
  • H. C. Cheng, R. S. Li, S. C. Lin, W. H. Chen and K. N. Chiang, "Macroscopic Mechanical Constitutive Characterization of Through-Silicon-via-Based 3-D Integration", IEEE Transactions on Components, Packaging, and Manufacturing Technology, Volume 6, Issue3, Pages 432-446, March 2016.
  • W. J. Lee, K. N. Chiang, V. Lebiga, and V. Fomin, "Interfacial Topography and Properties of Graphene Sheets on Different Reconstructed Silicon Surfaces", CARBON, Volume 96, Pages 29-39, January 2016.
  • K. C. Wu, S. Y. Lin, T. Y. Hung and K. N. Chiang, "Reliability Assessment of Packaging Solder Joints Under Different Thermal Cycle Loading Rates", IEEE Transactions on Device and Materials Reliability, Volume 15, Issue3, Pages 437–442, September 2015.
  • Y. Shao, B. Li, K. N. Chiang, S. Y. Liang, "Physics-based Analysis of Minimum Quantity Lubrication Grinding", International Journal of Advanced Manufacturing Technology, Volume 79, Issue 9, Pages 1659-1670, August 2015.
  • H. H. Chang, Y. F. Su, S. Y. Liang, K. N. Chiang, "The Effect of Mechanical Stress on Electromigration Behavior", Journal of Mechanics, Volume 31, Issue 4, Pages 441-448, August 2015.
  • W. H. Chen, C. F. Yu, K. N. Chiang, H. C. Cheng, "First-principles density functional calculations of physical properties of orthorhombic Au2Al crystal", Intermetallics, Volume 62, Pages 60–68, July 2015.
  • P. C. Chen, Y. F. Su, S. Y. Yang, S. Y. Liang, and K. N. Chiang, "Determination of Initial Crack Strength of Silicon Die Using Acoustic Emission Technique", Journal of Electronic Materials, Volume 44, Issue 7, Pages 2497-2506, May 2015.
  • S. Venkatachalam, O. Fergani, X. P. Li, J. G Yang, K. N. Chiang, S. Y. Liang, "Microstructure Effects on Cutting Forcesand Flow Stress in Ultra‐precision Machining of Polycrystalline Brittle Materials", ASME Journal of Manufacturing Sciences and Engineering, Volume 137, Issue 2, April 2015.
  • H. J. Wang, H. A. Deng, S. Y. Chiang, Y. F. Su, K. N. Chiang,"Development of a Process Modeling for Residual Stress Assessment of Multilayer Thin Film Structure", Thin Solid Films, Volume 584, Pages 146–153, June 2015.
  • P. C. Chen, Y. F. Su, S. Y. Yang, C. C. Lee, and K. N. Chiang, "Evaluation of Die Strength using Finite Element Method with Experiment Validation", IEEE Transactions on Components, Packaging, and Manufacturing Technology, Volume 4, Issue 7, Pages 1152-1158, July 2014.
  • L. L. Liao, T. Y. Huang, C. K. Liu, W. Li, M. J. Dai, and K. N. Chiang, "Electro-thermal finite element analysis and verification of power module with aluminum wire", Microelectronic Engineering, Volume 120, Pages 114–120, May 2014.
  • L. L. Liao, M. J. Dai, C. K. Liu, and K. N. Chiang, "Thermo-electric finite element analysis and characteristic of thermoelectric generator with intermetallic compound", Microelectronic Engineering, Volume 120, Pages 194–199, May 2014.
  • C. F. Huang, Y. F. Su, C. B. Lin, and K. N. Chiang,"Research on the degradation of AlGaInP Ultra High Brightness LEDs influenced by ohmic metal design," Microelectronic Engineering , Volume 120, Pages 182–187, May 2014.
  • C. C. Lee, C. H. Liu, R. H. Deng, H. W. Hsu, K. N.C hiang, " Investigation of consequent process-induced stress for N-type metal oxide semiconductor field effect transistor with a sunken shallow trench isolation pattern", Thin Solid Films, Volume 557, Pages 323–328, April 2014.
  • C. F. Huang; Y. F. Su; C. B. Lin; K. N. Chiang, "Research on Efficiency Droop Mechanism and Improvement in AlGaInP Ultra-High-Brightness LEDs Using the Transient Measurement Method", Solid-State Electronics, Volume 93, Pages 15-20, March 2014.
  • T. Y. Hung, L. L. Liao, C. C. Wang, W. H. Chi, and K. N. Chiang, "Life Prediction of High Cycle Fatigue in Aluminum Bonding Wires under Power Cycling Test", IEEE Transactions on device and materials reliability, Volume 14, Pages 484-492, March 2014.
  • Chang-Chun Lee, Yen-Fu Su, Chih-Sheng Wu, and Kuo-Ning Chiang, "Investigation of interconnect design on interfacial cracking energy of Al/TiN barriers under a flexural load," Thin Solid Films, Volume 544, Pages 530-536, October 2013.
  • C. J. Huang, T. Y. Hung, and K. N. Chiang, "Estimation of the Mechanical Property of CNT Ropes Using Atomistic-Continuum Mechanics and the Equivalent Methods," CMC:-Computers, Materials, & Continua, Volume 36, Pages 99-133, July 2013.
  • T. L. Chou, H. F. Hong, C. N. Han, and K. N. Chiang, "Thermal Performance Assessment and Validation of High Concentration Photovoltaic Solar Cell Module ," IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, Volume 2, Issue 4 Pages 578-586, April 2012.
  • Y. F. Su, S. Y. Yang, T. Y. Hung, C. C. Lee, and K. N. Chiang, "Light degradation test and design of thermal performance for high-power light-emitting diodes," Microelectronics Reliability, Volume 52, Issue 5, pp.794-803, 2012
  • C.C. Lee, H.H. Chang, C.C. Chiu, and K.N. Chiang,"Investigation of Stress Effect of Electromigration Behavior of Aluminum Strip," IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, Vol 1, issue 10 pp.1558-1563, OCT 2011.
  • T. Y. Hung, S. Y. Chiang, C. J. Huang, C. C. Lee, and K. N. Chiang, "Thermal-mechanical behavior of the bonding wire for a power module subjected to the power cycling test," Microelectronics Reliability, vol 51, issues 9-11, pp.1819-1823, 2011
  • T. L. Chou, S. Y. Yang, C. J. Wu, C. N. Han, and K. N. Chiang, “Measurement and simulation of interfacial adhesion strength between SiO2 thin film and III-V material,” Microelectronics Reliability, vol 51, issues 9-11, pp.1757-1761, 2011
  • T. L. Chou, S. Y. Yang, and K. N. Chiang, “Overview and applicability of residual stress estimation of film-substrate structure,” Thin Solid Films, Volume 519, Issue 22, 1 September 2011, Pages 7883-7894, ISSN 0040-6090
  • C. J. Huang, C. J. Wu, H. A. Teng, and K. N. Chiang , "A Robust Nano-Mechanics Approach for Tensile and Modal Analysis Using Atomistic-Continuum Mechanics Method" , Computational Materials Science, vol.50, pp.2245-2248, 2011.
  • S. Y. Chiang, T. L. Chou, Z. H. Shih, H. F. Hong, and K. N. Chiang, "Life Prediction of HCPV under Thermal Cycling Test Condition" , Microelectronic Engineering, Volume 88, pp.785-790, 2011.
  • C. J. Wu, M. C. Hsieh, C. C. Chiu, M. C. Yew, and K. N. Chiang, "Interfacial delamination investigation between copper bumps in 3D chip stacking package by using the modified virtual crack closure technique" , Microelectronic Engineering, Volume: 88, pp. 739-744, 2011.
  • W. H. Chi, T. L. Chou, C. N. Han, S. Y. Yang, K. N. Chiang, "Analysis of Thermal and Luminous Performance of MR-16 LED Lighting Module", IEEE Transactions on Components and Packaging Technologies, Vol.33, Issue: 4, pp.713-721, 2010.
  • C. C. Lee, C. C. Lee and K. N. Chiang, ”Electromigration Characteristic of SnAg3.0Cu0.5 Flip Chip Interconnection”, IEEE Trans. Adv. Packag, Volume 33, Issue 1, pp. 189-195, 2010.
  • C.Y. Chou, T.Y. Hung, C.J. Huang and K.N. Chiang, "Development Of Empirical Equations For Metal Trace Failure Prediction Of Wafer Level Package Under Board Level Drop Test," IEEE Trans. Adv. Packag, Volume 33, Issue 3, pp. 681-689, 2010.
  • C. C. Chiu, C.J. Huang, S.Y. Yang, C.C. Lee, and K.N. Chiang, "Investigation of the delamination mechanism of the thin film dielectric structure in flip chip packages," Microelectronic Engineering, vol. 87, pp. 496-500, 2010.
  • C. J. Wu, M.C. Hsieh, and K.N. Chiang, "Strength evaluation of silicon die for 3D chip stacking packages using ABF as dielectric and barrier layer in through-silicon via," Microelectronic Engineering, vol. 87, pp. 505-509, 2010.
  • Tzu-Sen Yang, Yujia Cui, Chien-Ming Wu, Jem-Mau Lo, Chi-Shiun Chiang,Wun-Yi Shu, Chung-Shan Yu, Kuo-Ning Chiang, and Ian C. Hsu, "Determining the Zero-Force Binding Energetics of Intercalated DNA Complex Using Single Molecule Approach," ChemPhysChem, 10, 2791-2794 2009.
  • Tsung-Lin Chou, Chien-Fu Huang, Cheng-Nan Han, Shin-Yueh Yang, and Kuo-Ning Chiang, “Fabrication Process Simulation and Reliability Improvement of High- brightness LEDs,” Microelectronics Reliability, Volume 49, Issue 9-11, pp. 1244-1249, 2009.
  • Tsung-Lin Chou, Chen-Hung Chu, Hsin-Nan Chiang, and Kuo-Ning Chiang, “Residual Stress and Thermal Effect of MEMS Pressure Sensor,” Electronic Monthly, Volume 168, pp. 150-167, July 2009. (in Chinese)
  • Ming-Chih Yew, Mars Tsai, Dyi-Chung Hu, Wen-Kun Yang, Kuo-Ning Chiang, "Reliability analysis of a novel fan-out type WLP," Soldering & Surface Mount Technology, Volume 21(3): p. 30-38 , 2009.
  • C. C. Lee, C. C. Chiu, C. C. Hsia, and K. N. Chiang, "Interfacial fracture analysis of CMOS Cu/Low-k BEOL interconnect in advanced packaging structures," IEEE Transactions on Advanced Packaging, Vol. 32, No.1, pp. 53-61, 2009.
  • C. J. Wu, C. Y. Chou, C. N. Han, and K. N. Chiang, "Estimation and Validation of Elastic Modulus of Carbon Nanotubes Using Nano-Scale Tensile and Vibrational Analysis," Computer Modeling in Engineering and Science, Vol. 41, No. 1, pp. 49-68, 2009.
  • M. C. Yew, C. C. A. Yuan, C. J. Wu, D. C. Hu, W. K. Yang, and Kuo-Ning Chiang, “Investigation of the Trace Line Failure Mechanism and Design of Flexible Wafer Level Packaging,” IEEE Transactions on Advanced Packaging, Volume, 32, No. 2, pp. 390-398, 2009.
  • Tsung-Lin Chou, Chen-Hung Chu, Chun-Te Lin and Kuo-Ning Chiang, “Sensitivity analysis of packaging effect of silicon-based piezoresistive pressure sensor,” Sensors & Actuators: A. Physical, Volume 152, Issue 1, pp. 29-38, 2009.
  • Kuo-Ning Chiang, Chan-Yen Chou, Chung-Jung Wu, Chao-Jen Huang, Ming-Chih Yew, "Analytical Solution for Estimation of Temperature-Dependent Material Properties of Metals Using Modified Morse Potential" , CMES-COMPUTER MODELING IN ENGINEERING & SCIENCES, Volume 37, Issue 1,pp. 85-96, 2008.
  • Chang-Chun Lee, Tai-Chun Huang, Chin-Chiu Hsia, and Kuo-Ning Chiang, “Interfacial Fracture Investigation of Low-k Packaging Using J-Integral Methodology,” IEEE TRANSACTIONS ON ADVANCED PACKAGING, Vol. 31, pp. 91-99, 2008
  • C. Y. Chou, T. Y. Hung, S. Y. Yang, M. C. Yew, W. K. Yang, and K. N. Chiang, "Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact," Microelectronics Reliability, Vol. 48, pp. 1149-1154, 2008.
  • C. C. Lee, T. L. Chou, C. C. Chiu, C. C. Hsia, and K. N. Chiang, "Cracking energy estimation of ultra low-k package using novel prediction approach combined with global–local modeling technique," Microelectronic Engineering, Vol. 85, Issue 10, pp. 2079-2084, 2008.
  • C. C. Chiu, C. C. Lee, T. L. Chou, C. C. Hsia, and K. N. Chiang, "Analysis of Cu/Low-k structure under back end of line process," Microelectronic Engineering, Vol. 85, Issue 10, pp. 2150-2154, 2008.
  • H. T. Ku, and K. N. Chiang, "The mechanical stress resistance capability of stress buffer structures in analog devices," Microelectronic Reliability, Vol. 48, pp. 716-723, 2008.
  • M. C. Yew, C. Y. Chou, and K. N. Chiang, "Reliability assessment for solders with a stress buffer layer using ball shear strength test and board-level finite element analysis." Microelectronics Reliability, Vol. 47, pp. 1658-1662, 2007.
  • C. C. Chiu, H. H. Chang, C. C. Lee, C. C. Hsia, and K. N. Chiang, "Reliability of interfacial adhesion in a multi-level copper/low-k interconnect structure," Microelectronics Reliability, Vol. 47, pp. 1506-1511, 2007.
  • C. T. Lin, and K. N. Chiang, "From atomic-level lattice structure to estimate the silicon mechanical bulk behavior using the atomistic-continuum mechanics," Key Engineering Materials, Vol 334-335 I, pp. 281-284, 2007.
  • S. M. Chang, C. Y. Cheng, L. C. Shen, K. N. Chiang, Y. J. Hwang, Y. F. Chen, C. T. Ko, and K. C. Chen, "A novel design structure for WLCSP with high reliability, low cost, and ease of fabrication," IEEE Transactions on Advanced Package, Vol. 30, No. 3, pp. 377-383, 2007.
  • C. C. Chiu, C. J. Wu, C. T. Peng, K. N. Chiang, T. Ku, and K. Cheng, "Failure life prediction and factorial design of lead-free flip chip package," Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers, Vol.30, No. 3, pp. 481-490, 2007.
  • C. C. Lee, H. C. Liu and K. N. Chiang, "3D Structure Design and Reliability Analysis of Wafer Level Package with Stress Buffer Mechanism," IEEE Transactions on Component and Packaging Technologies, Vol. 30, No.1, pp.110- 118, 2007.
  • C. A. Yuan, G. Q. Zhang, C. N. Han, and K. N. Chiang, "Numerical simulation on the mechanical characteristics of double-stranded DNA under axial stretching and lateral unzipping," J. Appl. Phys. 101, 074702, 2007.
  • C. C. Lee, S. M. Chang and K. N. Chiang, “Sensitivity Design of DL-WLCSP Using DOE With Factorial Analysis Technology”, IEEE Transaction of Advanced Packaging, Vol 30, No. 1, pp. 44-55, April 2007.
  • C. C. Lee, C. C. Lee, H. T. Ku, S. M. Chang, and K. N. Chiang, "Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology," Microelectronics Reliability, Vol. 47, pp. 196-204, 2007.
  • Chen, KM, Houng, KH, Chiang, KN, "Thermal resistance analysis and validation of flip chip PBGA packages", MICROELECTRON RELIAB 46 (2-4): 440-448 FEB-APR 2006
  • Chang, KC, Chiang, KN, "Growth analysis of interfacial delamination in a plastic ball grid array package during solder reflow using the global-local finite element model", J STRAIN ANAL ENG 41 (1): 19-30 JAN 2006.
  • K. N. Chiang, C. Y. Chou, and C. J. Wu, and C. A. Yuan, "Prediction of The Bulk Elastic Constant of Metals Using Atomic-Level Single-Lattice Analytical Method" Appl. Phys. Lett. 88, 171904, 2006.
  • K. N. Chiang , C.A. Yuan, C. N. Han, C. Y. Chou and Yujia Cui,"Mechanical Characteristic of ssDNA/dsDNA Molecule Under External Loading", Appl. Phys. Lett., 88, 023902, 2006, also published in the January 23, 2006 issue of Virtual Journal of Nanoscale Science & Technology.
  • K. N. Chiang , Chien Chen Lee, Chang Chun Lee and K. M. Chen, "Current crowding-induced electromigration in SnAg3.0Cu0.5 micro-bumps", Appl. Phys. Lett., 88 072102, 2006.
  • Ming-Chih Yew, Chien-Chia Chiu, Shu-Ming Chang and Kuo-Ning Chiang, "A Novel Crack and Delamination Protection Mechanism for a WLCSP Using Soft Joint Technology," Soldering & Surface Mount Technology, Vol. 18, Issue 3, 2006, pp. 3-13.
  • M. C. Yew, C. Y. Chou, C. S. Huang, W. K. Yang, K. N. Chiang, "The Solder on Rubber (SOR) Interconnection Design and Its Reliability Assessment Based on Shear Strength Test and Finite Element Analysis," Journal of Microelectronics Reliability, Vol. 46, 2006, pp. 1874-1879.
  • K. C. Chang and K. N. Chiang, "Growth Analysis of Interfacial Delamination of Plastic Ball Grid Array Package During Solder Reflow Using Global-Local Finite Element Method." Journal of Strain Analysis for Engineering Design, Vol. 41, No. 1, pp. 19-30, 2006.
  • Liu, C. M., Lee, C. C., Ku, H. T., Chiu, C. C., and Chiang, K. N., “Interconnect Design and Thermal Stress/Strain Analysis of Flip Chip Packaging,” Key Engineering Materials, pp.521, 2006. (EI)
  • Lee, C. C., Ku, H. T., Chiu, C. C., and Chiang, K. N., “A Novel Prediction Technique for Interfacial Crack Growth of Electronic Interconnect,” Key Engineering Materials, pp.533, 2006. (EI)
  • Liu, C. M., Lee, C. C., and Chiang, K. N., “Enhancing the Reliability of Wafer Level Packaging by Using Solder Joints Layout Design,” IEEE Transactions on Component and Packaging Technologies, Vol. 29, No. 4, pp. 877-885, 2006.
  • W. H. Chen, S. R. Lin and K. N. Chiang, "Predicting the Liquid Formation for the Solder Joints in Flip Chip Technology", ASME Transactions Journal of Electronic Packaging, Vol. 128, No. 4, pp. 331-338, 2006.
  • Liu, C. M., Lee, C. C., and Chiang, K. N., “Enhancing the Reliability of Wafer Level Packaging by Using Solder Joints Layout Design,” IEEE Transactions on Component and Packaging Technologies, Vol. 29, No. 4, pp. 877-885, 2006.
  • C. C. Lee, C. T. Peng, and K. N. Chiang, "Packaging Effect Investigation of CMOS Compatible Pressure Sensor Using Flip Chip and Flex Circuit Board Technologies,” Sensors and Actuators Journal A, Vol 126/1, pp 48-55, 2006.
  • K. M. Chen and K. N. Chiang, "Developing an Analytic Methodology to Accurately Predict Probing Depth in Integrated Circuit Structures". Journal of Electronic Materials, Vol. 35, pp.257-265, 2006.
  • C. C., Lee, and K. N. Chiang, “Design and Reliability Analysis of a Novel Wafer Level Package with Stress Buffer Mechanism,” Journal of the Chinese Institute of Engineers, Vol. 29, No. 3, pp. 433-443, May 2006. (SCI/EI)
  • C. T. Peng, C. T. Kuo, K. N. Chiang, Terry Ku, and Kenny Chang, "Experimental Characterization and Mechanical Behavior Analysis of Intermetallic Compounds of Sn-3.5Ag Lead-free Solder Bump with Ti/Cu/Ni UBM Copper Chip," Microelectronics Reliability, Vol. 46, Issue 2-4, pp. 523-534, 2006.
  • C. A. Yuan, C. N. Han, M. C. Yew, C. Y. Chou and K. N. Chiang, "Design, Analysis and Development of Novel Three-Dimensional Stacking WLCSP," IEEE Transaction of Advanced Packaging, Vol 28, No. 3, pp. 387-396, Aug. 2005.
  • Lin, J. C. and Chiang K. N., “Design and Analysis of Wafer-Level CSP with Double Pad Structure”, IEEE Transactions on Components and Packaging Technologies, Vol. 28, No. 1, pp. 117-126, March, 2005
  • C. C. Lee, K. N. Chiang, W. K. Chen, and R. S. Chen, “Design and Analysis of Gasket Sealing of Cylinder Head under Engine Operation Conditions,” Finite Elements in Analysis and Design, Vol. 41, No. 11-12, pp.1160-1174, Jun.2005.
  • K. N. Chiang, C. H. Chang and C. T. Peng, "Local-Strain Effects in Si/SiGe/Si Islands on Oxide". Appl. Phys. Lett, 87, 191901, 2005.
  • C. T. Peng, J. C. Lin, C. T. Lin, K. N. Chiang, "Performance and Package Effect of a Novel Piezoresistive Pressure Sensor Fabricated by Front-Side Etching Technology", Sensors and Actuators Journal A 119, pp. 28-37 2005.
  • Peng, C. T., Cheng, H. C. and Chiang, K. N., “Reliability Analysis and Design for the Fine-pitch Flip Chip BGA Packaging”, IEEE Transactions on Components and Packaging Technologies, Vol. 27, No. 4, pp. 684-693, Dec. 2004
  • Chang, K. C. and Chiang, K. N., “Aging Study on Interfacial Microstructure and Solder Ball Shear Strength of a Wafer-Level CSP with Au/Ni Metallization on a Cu Pad”, Journal of Electronic Materials, Vol. 33, No. 11, pp. 1373-1380, November 2004 (SCI, EI)
  • K-C Chang, M-K Yeh and K-N Chiang, "Hygrothermal Stress Analysis of Plastic Ball Grid Array Package During Solder Reflow", Journal of Mechanical Engineering Science, Vol. 218, No. 9, pp. 957-970, September 2004 (SCI, EI).
  • Chiang, K. N., "Design, Fabrication and Analysis of WIT wafer Level Packaging", Engineering Science & Technology Bulletin, Vol. 75, pp.18-21, Aug. 2004.
  • Cheng, H. C. and Chiang, K. N., “Process-dependent Contact Characteristics of NCA Assemblies”, IEEE Transactions on Components and Packaging Technologies, Vol. 27, NO. 2, pp. 398-410, June 2004.
  • Chang, K. C. and Chiang, K. N., ”Improvements of Solder Ball Shear Strength of a Wafer-Level CSP Using a Novel Cu Stud Technology”, IEEE Transactions on Components and Packaging Technologies, Vol. 27, NO. 2, pp.373-382, June 2004.
  • Kuo, C. T., Yip, M. C. and Chiang, K. N., “Time and Temperature Dependent Mechanical Characterization of Polymer-Based Materials in Electronic Packaging Application”, Journal of the Chinese Institute of Engineers, Vol. 27, No. 7, pp. 949-954, 2004.
  • Peng, C. T. and Chiang, K. N., “Analysis and Validation of Thermal and Packaging Effects of a Piezoresistive Pressure Sensor”, Journal of the Chinese Institute of Engineers, Vol. 27, No. 7, pp. 955-964, 2004.
  • Lin, C. T. and Chiang, K. N., “Reliability Analysis of Flip Chip Packages Using the Contact Finite Element Method”, Journal of the Chinese Institute of Engineers, Volume 27, No. 2, pp.165-172, 2004.
  • Yuan, C. A. and Chiang, K. N., “Micro to Macro Thermo-Mechanical Simulation of Wafer Level Packaging”, ASME Transaction, Journal of Electronic Packaging, Volume 125, Issue 4, pp. 576-581, 2003.
  • Chang, K. C. and Chiang, K. N., “Solder Joint Reliability Analysis of a Wafer-Level CSP Assembly with Cu Studs Formed on Solder Pads”, Journal of the Chinese Institute of Engineers, 26/4, pp. 467-479, 2003.
  • Chen K. M. and Chiang, K. N., “Impact of Probing Procedure on Flip Chip Reliability”, Journal of Microelectronics Reliability, Vol.43, pp.123-130, 2003.
  • Lin, Y. T, Peng, C. T. and Chiang, K. N., "Parametric Design and Reliability Analysis of WIT Wafer Level Packaging", MICROELECTRON RELIAB 46 (2-4) Vol. 124, No.3, pp.234-239, Sept. 2002.
  • Lin, Y. T, Peng, C. T. and Chiang, K. N., "Parametric Design and Reliability Analysis of WIT Wafer Level Packaging", ASME Transaction, Journal of Electronic Packaging, Vol. 124, No.3, pp.234-239, Sept. 2002.
  • Chiang K. N.,"Design of WLCSP and MEMS devices”, No. 14, Journal of Electronis and Materials. May, 2002.
  • Yeh, M. K., Chiang, K. N. and Su, J. A., “Thermal Stress Analysis of Thermally-Enhanced Plastic Ball Grid Array Electronic Packaging”, The Chinese Journal of Mechanics, Vol. 18, No.1, pp.9-16, March 2002.
  • Chen W. H., Chiang K. N. and Lin S. R., "Prediction of Liquid Formation for Solder and Non-Solder Mask Defined Array Packages", ASME Transaction, Journal of Electronic Packaging, Vol.124, pp.37-43, 2002.
  • Chen, K. M., Houng, K. H. and Chiang, K. N. "Coplanarity Analysis and Validation of PBGA and T2-BGA Packages", Finite Elements in Analysis and Design, 38 (2002) pp.1165-1178.
  • Chiang K. N., Liu, C. N. and Peng, C. T., "Parametric Reliability Analysis of No-Underfill Flip Chip Package", IEEE Transactions on Components and Packaging Technologies, Vol.24, No.4, pp.635-640, Dec. 2001.
  • Chiang K. N. and Yuan C. A., "An Overview of Solder Bump Shape Prediction Algorithms with Validations", IEEE Transactions on Advanced Packaging, Vol.24, No.2, pp.158-162, May, 2001.
  • Chiang, K.N. Chang C. W. and J. D. Lin, " Process Modeling and Thermal/Mechanical Behavior of ACA/ACF type Flip-Chip Packages", ASME Transaction, Journal of Electronic Packaging, Vol. 123, pp.331-337, 2001.
  • Lin J. C. and Chiang K. N., "Thermal/Mechanical Analysis of Novel C-TSOP Using Nonlinear FEM Method", Journal of the Chinese Institute of Engineers, Vol. 24, No. 4, pp.453-462, 2001.
  • Chiang K. N., and Liu C. M., " A Comparison of Thermal Stress/Strain Behavior of Elliptical/Round Solder Pads", ASME Transaction, Journal of Electronic Packaging, Vol. 123, pp.127-131, June, 2001.
  • Cheng H. C., Chiang K. N., Cheng, C. K. and Lin J. C., "Study of Factor Affecting Solder Joint Fatigue Life of Thermally Enhanced Ball Grid Array Assemblies", Journal of the Chinese Institute of Engineers, Vol. 24, No. 4, pp.439-451, 2001.
  • Cheng H. C., Chiang K. N. and Chen T. Y., "Topology Optimization of Elastic Structures for Stability", A Journal of the Chinese Society of Mechanical Engineers, Vol.22, No.5, pp.391-398, 2001.
  • Chiang K. N., Lin Y. T. and Cheng H. C., "On Enhancing Eutectic Solder Joint Reliability Using a Second-Reflow-Process Approach", IEEE Transactions on Advanced Packaging, Vol. 23, No. 1, pp.9-14, Feb. 2000.
  • Chiang K. N., "Eutectic Solder Joint Reliability Analysis of Electronic Packages",Electronic Monthly, No. 52,pp.108-116,Nov. 1999.
  • Cheng H. C., Chiang K. N., and Lee M. H., "An Alternative Local/Global Finite Element Approach for Ball Grid Array Typed Packages", ASME Transaction, Journal of Electronic Packaging, Vol. 120, pp.129-134, June 1998.
  • Cheng H.C., Chiang K.N, and Lee M.H., "On the Optimal Topological Design of Plate/Shell Like Structures for Frequency Response Optimization Problems", The Chinese Journal of Mechanics, Vol. 14, No. 1, March 1998
  • Chiang K. N., Chen W. L., "Electronic Packaging Reflow Shape Prediction for The Solder Mask Defined Ball Grid Array", ASME Transaction, Journal of Electronic Packaging, Vol. 120, 175-178, 1998.
  • Chen, P. T., Chiang, K. N., Shyu, B. L., and Fu, S. H., "An Application of Coupled Finite Element Method/Boundary Element Method to The Computation of Structural Acoustic Response for Submerged Elastic Structures", Journal of The Society of Naval Architects and Marine Engineers, Vol. 16, No.4, pp.63-72, 1997.
  • Komzsik L. and Chiang K. N., "The Effect of a Lagrange Multiplier Approach in MSC/NASTRAN on Large Scale Parallel Applications", International Journal of Computing System in Engineering, Vol.4 No.2/4, 1993
  • Chiang K. N. and Fulton R. E., "Parallel Transient Finite Element Analysis", Journal of Computers and Structures, Vol. 42 No. 5, pp. 733-739, 1992.
  • Fulton R. E., Chiang K. N. and Ou R. F., "Parallel Nonlinear Finite Element Dynamic Response", International Journal of Computing System in Engineering, Vol.2, No. 2/3, pp. 243-252, 1991.
  • Chiang K. N. and Fulton R. E., "Structural Dynamics Methods for Concurrent Processing Computers", Journal of Computers and Structures, Vol. 36, No. 6, pp.1031-1037, 1990.
  • Fulton R. E. and Chiang K. N., "Concepts and Implementation of Parallel Finite Element Analysis", Journal of Computers and Structures, Vol. 36, No. 6, pp. 1039-1046, 1990.

 

 

Ph.D. Thesis

  • Chiang K. N., "Parallel Processing Approach for Crash Dynamic Analysis", Ph.D. Thesis, School of Mechanical Engineering, Georgia Institute of Technology, Atlanta, GA, Sept. 1, 1989.

 

Patents

  1. TW Patent No.I636537"扇出型多晶片堆疊封裝之電子裝置及形成該裝置之方法FAN-OUT MULTI-CHIP STACKING ASSEMBLY STRUCTURE AND MANUFACTURING METHOD" (107年獲認證)
  2. TW Patent No.I441312"具有打線結構之三維立體晶片堆疊封裝結構A THREE DIMENSIONAL CHIP STACKING ELECTRONIC PACKAGE WITH BONDING WIRES" (103年獲認證)
  3. TW Patent No.I426585 "具結構強化設計之電子封裝結構 AN ELECTRONIC PACKAGING STRUCTURE WITH ENHANCED DESIGN" (103年獲認證)
  4. TW Patent No.I395318 "使用嵌入式晶片載板之薄型立體堆疊封裝結構 THIN STACK PACKAGE USING EMBEDDED-TYPE CHIP CARRIER (102年獲認證)
  5. US Patent No. 7,884,464.“3D electronic packaging structure having a conductive support substrate” (100年認證)
  6. CN Patent No.101207101-A. “Pattern shielding structure for dry etching and method thereof” (99年認證)
  7. US Patent No. 6,023,097. “Stacked MCM uBGA Package” (99年認證)
  8. US Patent No. 6,137,174 “Hybrid ASIC/Memory Module Package” (99年認證)
  9. DE Patent No.102007061161-A1.“Elektronische 3D-Packungsstruktur mit einem leitenden Trägersubstrat” (98年認證)
  10. CN Patent No.101207101.“3D ELECTRONIC PACKAGING STRUCTURE WITH ENHANCED GROUNDING PERFORMANCE AND EMBEDDED ANTENNA” (97年認證)
  11. DE Patent No.102007061563-A1.“Elektronische 3D-Packungsstruktur mit verbesserter Erdungsleitung und eingebauter Antenne” (97年認證)
  12. JP Patent No. 2008-211175. “3d packaging structure with enhanced grounding performance and built-in antenna” (97年認證)
  13. KR Patent No. 1020070133799. “3d electronic packaging structure with enhanced grounding performance and an embedded antenna, for enhancing operation frequency and efficiency of a stack packaging module” (97年認證)
  14. US Patent 20080142941 “3D ELECTRONIC PACKAGING STRUCTURE WITH ENHANCED GROUNDING PERFORMANCE AND EMBEDDED ANTENNA” (97年認證)
  15. US Patent No. 7,211,886. “Three-dimensional multichip stack electronic package structure” (96年認證)
  16. Taiwan Patent No.I269460/TW 094134866, "具導電特性支撐底板之立體堆疊封裝結構 A 3D ELECTRONIC PACKAGING STRUCTURE USING CONDUCTIVE SUBSTRATE" (95年認證)
  17. Taiwan Patent No.I264103/TW 094146062, "強化接地特性與內埋天線型之立體堆疊封裝結構 A 3D ELECTRONIC PACKAGING STRUCTURE WITH ENHANCED GROUNDING PERFORMANCE AND EMBEDDED ANTENNA" (95年認證)
  18. Taiwan Patent No.I248669/TW 093105520, "三維高密度多微電子元件之晶圓級系統封裝結構 THREE-DIMENSIONAL HIGH-DENSITY OF WAFER LEVEL STRUCTURE OF SYSTEM PACKAGING WITH PLURAL MICROELECTRONIC DEVICES" (95年認證)
  19. Taiwan Patent No.I237276, "具有光波導之掃描探針式/近場光學式顯微鏡用之探針 PROBE WITH LIGHT WAVEGUIDE FOR THE SCANNING PROBE/SCANNING NEAR-FIELD OPTICAL MICROSCOPY" (94年認證)
  20. Taiwan Patent No.I234859, "多晶片堆疊立體電子構裝結構 THREE-DIMENSIONAL STACKING PACKAGING STRUCTURE" (94年認證)
  21. Taiwan Patent No.I233192, "堆疊多重封裝單元之晶圓級系統封裝結構 THE WAFER LEVEL STRUCTURE OF SYSTEM PACKAGING WITH STACKED PACKAGING UNITS" (94年認證)
  22. US Patent No. 6,034,425. “Flat MCM uBGA Package” (93年認證)
  23. US Patent No. 6,781,225. “Glueless integrated circuit system in a packaging module” (93年認證)
  24. Taiwan Patent No.I225381/TW 092133787, "具基板側凸塊結構之電子構裝結構 ELECTRONIC PACKAGING STRUCTURE WITH COMPOSITE BUMP AT SUBSTRATE SIDE" (93年認證)
  25. Taiwan Patent No.I220695, "晶片電訊檢測組件結構 ELECTRONIC TESTING STRUCTURE ASSEMBLY" (93年認證)
  26. Taiwan Patent No.I220803, "燃料電池之可調式端板組件結構 THE ADJUSTABLE END PLATE STRUCTURES FOR THE FUEL CELLS" (93年認證)
  27. Taiwan Patent No.200359, "多晶片平面微型球閘陣列包裝" (93年認證)
  28. US Patent No. 6,541,834 "Silicon pressure micro-sensing device and the fabrication process" (92年認證)
  29. Taiwan Patent No.177789, "晶圓級測試卡之探針結構" (92年認證)
  30. Taiwan Patent No.170790, "具複數個接觸單元之電訊測試組件結構" (92年認證)
  31. Taiwan Patent No.168114, "緩衝式雙墊片晶圓級封裝結構" (91年認證)
  32. Taiwan Patent No.165428, "低熱應力與高靈敏度點對點接合之微感測器結構" (91年認證)
  33. Taiwan Patent No.163153, "矽材壓力微感測元件及其製造方法" (91年認證)
  34. Taiwan Patent No.161310, "多晶片立體包裝" (91年認證)
  35. Taiwan Patent No.494718, "多單元多晶片微電子包裝(追加一)" (91年認證)
  36. Taiwan Patent No.155648, "以晶片之導電墊片耦合於佈線基材之導電墊片之封裝" (91年認證)
  37. Taiwan Patent No.150448, "發泡陣列微晶片之封裝結構" (91年認證)
  38. Taiwan Patent No.143037, "無封膠陶瓷基材覆晶封裝IC元件模組" (90年認證)
  39. Taiwan Patent No.132565, "具有散熱背板之覆晶模組封裝機構" (90年認證)
  40. Taiwan Patent No.125001, "多晶片堆疊微型球閘陣列包裝" (89年認證)
  41. Taiwan Patent No.126708, "具有多晶片堆疊封裝之電子裝置及形成該裝置之方法" (89年認證)
  42. Taiwan Patent No.122698, "平面多晶片微電子包裝" (89年認證)
  43. Taiwan Patent No.200929590, "多層散熱板之光電元件結構 A PHOTOELECTRIC DEVICE STRUCTURE WITH MULTI-LAYER THERMAL DISPERSION PLATES"
  44. Taiwan Patent No.200612588, "利用應力控制使積體電路元件匹配之方法及其應用 METHOD AND APPLICATIONS OF STRESS-CONTROLLED ELECTRICAL DEVICE MATACHING IN INTEGRATED CIRCUIT"
  45. Taiwan Patent No.200610078, "使用形成於銲錫接墊上金屬銷子進行封裝之方法 PACKAGING WITH METAL STUDS FORMED ON SOLDER PADS"
  46. Taiwan Patent No.200413537, "可重複使用之生技檢測結構 A REUSABLE BIO-MEASUREMENT DEVICE"

 

 

Book and Technical Report

  1. Chiang K. N. "Encyclopedia of Thermal Stresses", Springer ISBN 978-94-007-2739-7, 2013.
  2. Chiang K. N. "Nano-Bio-Electronic, Photonic and MEMS Packaging", Springer ISBN 978-1-4419-0039-5, 2010.
  3. Chiang K. N. "微電子系統封裝基礎理論與應用技術" 滄海書局, 2006.
  4. Chiang K. N.,"晶圓級與微機電封裝之設計準則與未來走向", No. 14, 電子與材料季刊, May, 2002.
  5. Chiang K. N., "Eutectic Solder Joint Reliability Analysis of Electronic Packages",Electronic Monthly, No. 52,pp.108-116,Nov. 1999.
  6. Chiang K. N., "電子封裝與力學",第五屆力學教學研討會─力學教學與現代科技專刊,pp.112-115,Dec.10, 1998
  7. Chiang K. N., "電子構裝與計算力學", 中華民國力學學會會訊81期, pp. 1-13, Dec. 1997.
  8. Ume C., Yeh C. P. and Chiang K. N. (Editors),"Sensing, Modeling and Simulation in Emerging Electronic Packaging", EEP-Vol.17, ASME, 1996. (EI)
  9. Chiang K. N., "MSC/NASTRAN Kernels, Testers, and Timers Version 67.5Vol. I", The MacNeal-Schwendler Co. Book Series, April 1993.
  10. Chiang K. N., "MSC/NASTRAN Kernels, Testers, and Timers Version 67.5Vol. II", The MacNeal-Schwendler Co. Book Series, April 1993
  11. Fulton R. E, Chiang K. N., "A General Approach to Nonlinear Dynamic Analysis on Parallel/Vector Computers", Visualization in Supercomputing pp.41-63, Lecture Series in Engineering, Springer-Verlag, 1990.
  12. Fulton, R. E. and Chiang, K. N., "Computational Crash Dynamics Methods for Fifth Generation Supercomputers", General Motors Research Labs. technical report phase II (E-25-633), Jan. 1988.
  13. Fulton, R. E. and Chiang, K. N., "Computational Crash Dynamics Methods for Fifth Generation Supercomputers". General Motors Research Labs. technical report phase III (E-25-633), Dec. 1988.
  14. Fulton, R. E. and Chiang, K. N., "Computational Crash Dynamics Methods for Fifth Generation Supercomputers", General Motors Research Labs. report phase I (E-25-633), Dec. 1986.
  15. Fulton R. E., Goehlich D., Runfu Ou and Chiang Kuo-Ning, "Structural Dynamics Methods for Parallel Supercomputers", The MacNeal-Schwendler Co. and Georgia Institute of Technology Contract Technical Report Phase III, Oct. 1989.

 

Awards and Honors

  • Distinguished Research Award (2003-2006, 2010-2013, 2015-2018 國科會傑出研究獎) – National Science Council, Taiwan (Counterpart of National Science Foundation, US)
  • Co-Editor-in-Chief, IEEE Transaction on Components, Packaging and Manufacturing Technologies (2011-present)
  • Editor-in-Chief, Journal of Mechanics (2011 – present)
  • Corresponding Member (2013), Russian International Academy of Engineering
  • IEEE Fellow (2013)
  • STAM Fellow (2012)
  • ASME Fellow (2004)
  • Board of Governors, IEEE-CPMT (2013-2016)
  • Chair Professor of National Tsing Hua University, 2013-
  • CDistinguished Professor of National Tsing Hua University, 2007-2013
  • Associate Editor, IEEE Transaction on Advanced Packaging (2008-2011)
  • Associate Editor, IEEE Transaction on Components and Packaging Technologies (2006-2011)
  • Associate Editor of Journal of Electronic Packaging – ASME Transactions, 2006-2011
  • Associate Editor of Journal of Mechanics, 2006-present
  • Significant Contribution Award for "Advanced Packaging Technologies", IEEE 2009 International Conference on Electronic Packaging Technology
  • Excellent Contribution Award for "Simulation and modeling of micro/nanoelectronics and systems", IEEE 2009 International Conference on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro/Nanoelectronics and Systems
  • Distinguished Scholar Research Project Award – National Science Council, Taiwan, 2008-2010
  • Distinguished Industry-Academy Cooperation Award – National Tsing-Hua University, Taiwan, 2008
  • Best Paper Award, 2011 IEEE, International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT2011).
  • NXP Semiconductor Best Paper Award, 2008 IEEE, International Conference on Electronic Packaging Technology – High Density Packaging
  • Best Paper Award, 2008 IEEE, International Microsystems, Packaging, Assembly and Circuits Technology Conference – Electronic Materials and Packaging Technology.
  • Best Paper Award, 2007 IEEE, International Conference on Electronics Materials and Packaging (EMAP 2007)
  • Best Paper Award, 2007 IEEE, International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT 2007)
  • Best Paper Award (2005) – ANSYS Conference
  • Excellent Journal Paper Award (1998) – “On the Optimal Topological Design of Plate/Shell Like Structures for Frequency Response Optimization Problems”
  • Best Paper Journal Award (1997) – “An Application of Coupled Finite Element Method/Boundary Element Method to The Computation of Structural Acoustic Response for Submerged Elastic Structures”
  • Honorary General Program Chair, IMPACT2012,2013 (International Microsystems, Packaging, Assembly and Circuits Technology Conference)
  • General Program Co-Chair, IMPACT2010 (International Microsystems, Packaging, Assembly and Circuits Technology Conference, IEEE/IMAPS)
  • General Co-Program Chair, IMPACT2006 International Conference (IEEE/IMAPS)
  • General Co-Program Chair, IMPACT2007 International Conference (IEEE/IMAPS)
  • General Co-Program Chair, IMPACT2008 International Conference (IEEE/IMAPS)
  • General Co-Program Chair, IMPACT2009 International Conference (IEEE/IMAPS)
  • General Co-Program Chair, EMAP2009 (International Conference on Electronic Materials and Packaging, IEEE/IMAPS)
  • General Co-Program Chair ICEPT2006,2007 (International Conference on Electronic Packaging Technology, IEEE)
  • Technical Program Chair, IMPACT2006 (IEEE/ASME/IMAPS)
  • International Liaison, ITherm2004, 2006, 2008, 2010, 2012 International Conference(IEEE)
  • Technical committee, EPTC2004-2013 (IEEE)
  • Plenary Speaker, 2008 IEEE International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT2008)
  • Plenary Speaker, 2006 IEEE, International Conference on Electronic Packaging Technology (ICEPT2006)
  • Keynote Speaker, 2004 IEEE International Conference on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro/Nanoelectronics and Systems (EuroSimE2004)
  • Keynote Speaker, 2005 International Conference on Computational & Experimental Engineering and Sciences
  • Plenary Speaker, ANASYS2008
  • First Section Chair and Secretary-General of ASME-Taiwan Section, 2000-2003
  • Chairman of International Microelectronic and Packaging Society (IMAPS) – Taiwan Chapter, 2006-present
  • President of Taiwan Microelectronic and Packaging Society, 2006-present
  • Valued Reviewer in 2009, Journal of Sensors and Actuators A
  • General Program Chair – ANSYS2008
  • Director, Advanced Packaging Research Center, NTHU, 2005-present
  • Technical Committee of ASME Electronic & Photonic Packaging Division, 2009-present
  • Founder and Secretary-General of Chinese Computer-Aided Engineering Association, 1996
  • Chairman of Key Application Committee, ITRI/Electronics Research and Service Organization, 2004-present
  • Editorial Advisory Board, Journal Sensor Letters, 2001