Conference papers

  1. Y. C. Chen, H. L. Chen and K.N. Chiang, "Combing Process Modeling and Machine Learning Technology to Predict the Warpage of THe Panel-Level Packaging After Debonding", IMPACT 2023, Taipei, Taiwan, Oct. 25, 2023.
  2. Q. Su and K.N. Chiang, ''Fitting Solder305 Anand Model Parameters with Artificial Neural Networks", IMPACT 2023, Taipei, Taiwan, Oct. 26, 2023.
  3. C. E. Lee, Cadmus Yuan and K.N. Chiang, ''Use Artificial Neural Network to fit stress-strain curve of Chaboche model on lead-free solder SAC305", IMPACT 2023, Taipei, Taiwan, Oct. 26, 2023.
  4. Cadmus Yuan, J. Y. Wang, C. E. Lee and K.N. Chiang, "Equation Informed Neural Networks with Bayesian Inference Improvement for the Coefficient Extraction of the Empirical Formulas", EuroSimE 2023, Graz, Austria, April 16-19, 2023.
  5. C. Y Chang and K.N. Chiang, "Using Grid Search Methods and Parallel Computing to Reduce AI Training Time for Reliability Lifetime Prediction of Wafer-Level Packaging" EuroSimE 2023, Graz, Austria, April 16-19, 2023.
  6. Z. Shu and K.N. Chiang, "Studying Asymmetric Warpage Behavior of Panel-Level Packages Using Process Modeling Techniques and Viscoelasticity Theory", EuroSimE 2023, Graz, Austria, April 16-19, 2023.
  7. H. L. Chen and K.N. Chiang, "The Effect of Geometric and Material Uncertainty on Debonding Warpage in Fan-Out Panel Level Packaging", EuroSimE 2023, Graz, Austria, April 16-19, 2023.
  8. J. Y. Wang, Cadmus C. A. Yuan and K. N. Chiang, "Wire Boning Process Failure Risk Estimation of the Culow-k Structure using the Transient Finite Element", IMPACT 2022, Taipei, Taiwan, Oct. 26-28, 2022.
  9. P. Y. Sun, Cadmus C. A. Yuan and K. N. Chiang, "The numerical study of mechanical improvement of the metal annealing process during the manufacturing of the IC backend Damascene structure", IMPACT 2022, Taipei, Taiwan, Oct. 26-28, 2022.
  10. Z. Shu, B. S. Wang and K.N. Chiang, "Using Extra Trees Machine Learning Algorithm to Predict the Asymmetric Warpage Geometry of Panel Level Packaging", IMPACT 2022, Taipei, Taiwan, Oct. 26-28, 2022.
  11. C. Y Chang, H. M. Chang and K.N. Chiang, "Predict Reliability Life of Wafer Level Packaging Using GPR with Cluster Analysis", IMPACT 2022, Taipei, Taiwan, Oct. 26-28, 2022.
  12. H. L. Chen, B. S. Chen, and K. N. Chiang, "Predict the Reliability Life of Wafer Level Packaging using K-Nearest Neighbors algorithm with Cluster Analysis", IMPACT 2022, Taipei, Taiwan, Oct. 26-28, 2022.
  13. H. H. Liao and K. N. Chiang, "Research on Polynomial Regression Machine Learning Model with K-Means Algorithm for Predicting Advanced Packaging Reliability", ICEP 2022, Sapporo, Japan, May. 11-14, 2022.
  14. Y. W. Huang and K. N. Chiang, "Study of Shear  Locking Effect on 3D Solder Joint Reliability Analysis", IMPACT 2021, Taipei, Taiwan, Dec. 21-23, 2021.
  15. S. K. Panigrahy and K. N. Chiang, "A Machine Learning based Polynomial Regression model used for Predict Reliability life of wafer Level Package", IMPACT 2021, Taipei, Taiwan, Dec. 21-23, 2021.
  16. H. M. Chang, B. W. Chen, and K. N. Chiang, "The effect of data distribution in Ensemble Learning Algorithms on WLCSP reliability Prediction", IMPACT 2021, Taipei, Taiwan, Dec. 21-23, 2021.
  17. B. S. Wang, G. R. Huang, and K. N. Chiang, "PSO-based Modified Convolution Neural Network on Fan-Out Panel Level Package Prediction", IMPACT 2021, Taipei, Taiwan, Dec. 21-23, 2021.
  18. G. R. Huang, M. Y. Chen, and K. N. Chiang, "Prediction of Fan-Out Level Packaging Warpage using PSO-based Modified Convolutional Neural Network model with Laplacian Filter", ICEP 2021(Online event), May. 12-14, 2021.
  19. S. K. Panigrahy and K. N. Chiang, "Study on an Artificial Intelligence Based Kernel Ridge Regression Algorithm for Wafer Level Package Reliability Prediction", ECTC 2021, USA, 1 June-4 July, 2021.
  20. S. Y. Fu, Y. C. Tseng, and K. N. Chiang, "Study on Data Effect of Using RNN Model to Predict Reliability Life of Wafer Level Packaging", IMPACT-EMAP 2020, Taipei, Taiwan, October 21-23, 2020.
  21. G. R. Huang, M. Y. Chen, and K. N. Chiang, "Development of Modified Convolution Neural Network Model for Panel Level Warpage", IMPACT-EMAP 2020, Taipei, Taiwan, October 21-23, 2020.
  22. B. W. Chen, T. H. Tsai, and K. N. Chiang, "Investigation of data distribution effect in Random Forest Machine Learing Algorithm for WLCSP Reliability Prediction", IMPACT-EMAP 2020, Taipei, Taiwan, October 21-23, 2020.
  23. H. C. Kuo, B. R. Lai, and K. N. Chiang, "Study on Reliability Assessment of Wafer Level Package Using Design-on-Simulation with Support Vector Regression Techniques", IMPACT-EMAP 2020, Taipei, Taiwan, October 21-23, 2020.
  24. S. K. Panigrahy and K. N. Chiang, "Reliability Assessment of Wafer Level Packaging using K-Nearest Neighbor Regression Model", IMPACT-EMAP 2020, Taipei, Taiwan, October 21-23, 2020.
  25. Y. W. Huang and K. N. Chiang, "Reliability Assessment of Thermal Induced Creep Failure of WLCSP", IMPACT-EMAP 2020, Taipei, Taiwan, October 21-23, 2020.
  26. S. W. Liu, S. K. Panigrahy and K. N. Chiang, "Prediction of Fan-out Panel Level Warpage using Neural Network Model with Edge Detection Enhancement", 2020 ECTC, Florida(Virtual Conference), USA, June 3-30, 2020.
  27. B. R. Lai, Y. T. Shen, S. K. Panigrahy and K. N. Chiang, "AI-Assisted Design-on-Simulation Technology for Advanced Packaging", 2019 EMAP ,Busan, Korea, November 13-15, 2019
  28. T. H. Tsai, Y. T. Shen and K. N. Chiang, "Reliability Prediction of WLCSP using RF Regression Model", 2019 EMAP, Busan , Korea, November 13-15, 2019.
  29. Y. C. Tseng, Y. C. Lee and K. N. Chiang, "Reliability Prediction of WLP using AI Recurrent Neutal Network Regression Model", 2019 IMPACT, Taipei,Taiwan, Oct 23-Oct 25.
  30. M. Y. Chen, S. W. Liu and K. N. Chiang, "Prediction of Panel Level Warpage Using Convolution Neural Network Model", 2019 IMPACT, Taipei, Taiwan, Oct 23-Oct 25.
  31. S. K. Panigrahy, Y. T. Shen and K. N. Chiang, "Reliability Assessment of Wafer Level Packaging using Support Vector Regression Model", 2019 IMPACT, Taipei, Taiwan, Oct 23-Oct 25.
  32. T. H. Tsai, Y. T. Shen, and K. N. Chiang, "Reliability Prediction of WLCSP using RF Regression Model", ICEPT 2019, Hong Kong, Aug. 11-15, 2019.
  33. P. H. Chou, H. Y. Hsiao and K.N. Chiang, "Failure Life Prediction of Wafer Level Packaging using DoS with AI Technology" Electronic Components Technology Conference (ECTC 2016), Las Vegas, NV, USA, May 28-31, 2019.
  34. Y. C. Lee and K. N. Chiang, ”Reliability Assessment of WLCSP using Energy Based Model with Inelastic Strain Energy Density”, ICEP2019, Kuwana, Japan, April 17-21, 2019.
  35. S. W. Liu, C. H. Tsai, K. N. Chiang, ”Warpage and Simulation Analysis of Panel Level FO-WLCSP Using Equivalent CTE”, ICEP2019, Kuwana, Japan, April 17-21, 2019.
  36. Y. H. Liu, Y. T. Shen, and K. N. Chiang, “Trace line Layout Design of FO-WLCSP”, ICEP2019, Kuwana, Japan, April 17-21, 2019.
  37. H. Y. Hsiao, K. N. Chiang. “Reliability Assessment of Wafer-Level Packaging using Random Forest Regression Model”, 2018 IMPACT, Oct 24- Oct 26, Taipei, Taiwan.
  38. P. H. Chou, K. N. Chiang. “Reliability Assessment of Wafer Level Package using Artificial Neural Network Regression Model”, 2018 IMPACT, Oct 24- Oct 26, Taipei, Taiwan.
  39. T. N Chang, A. Huang, K. C. Wu, P. L. Wu, Y. T. Shen, P. H. Wang and K.N. Chiang, “Reliability Evaluation of I/O Pad Size Effect of FO-WLCSP”, 2018IMPACT, Oct 24- Oct 26, Taipei, Taiwan.
  40. V. Ramachandran, K. C. Wu, C. C. Lee and K. N. Chiang, "Reliability Life Assessment of WLCSP using Different Creep Models", ECTC 2018, May 29-June 1, 2018, San Diego, CA, USA.
  41. C. C. Chang, S. D. Lin and K. N. Chiang, "Empirical High Cycle Fatigue Life Prediction Model for Polysilicon MEMS", Materials for advanced metallization (MAM) 2018, Milan, Italy, March 18-21, 2018.
  42. P. H. Wang, A. Huang and K. N. Chiang ,"Design And Reliability Assessment of Stacked FAN-OUT Packaging", SMTA Pan Pacific Microelectronics Conference, Hawaii, USA, February 5-8, 2018.
  43. S. D. Lin and K. N. Chiang, “Study on High-Cycle Fatigue Behavior of Silicon Thin Film”, EMAP2017, Kunibiki Messe, Japan, Sept. 25-28, 2017.
  44. C. Y. Tsou, T. N Chang, K. C. Wu, P. L. Wu and K.N. Chiang, “Reliability Assessment using Modified energy based model for WLCSP Solder Joints”, ICEP2017, Yamagata, Japan, April 19-22, 2017.
  45. T. N. Chang, C. Y. Tsou, B. H. Wang, K. N. Chiang,” Novel wafer level packaging for large die size device”, ICEP2017, Yamagata, Japan, April 19-22, 2017.
  46. M. H. Hsu, K. N. Chiang and C. C. Lee, "A Modified Acceleration Factor Empirical Equation for BGA Type Package", ECTC2017, Orlando, USA, May 29 - June 2, 2017.
  47. Pei-Lun Wu, Pao-Hsiung Wang , Min-Hsuan Hsu and Kuo-Ning Chiang"Finite element mesh size effect for reliability assessment of WLCSP using different creep theories", 2016 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).
  48. Velsankar Ramachandran and Kuo-Ning Chiang"Characteristic study of anand and modified anand creep models for area array type WLCSP", 2016 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).
  49. K. C. Wu, C. H. Lee, and K. N. Chiang, "Characterization of thermal cycling ramp rate and dwell time effects on AF (Acceleration Factor) Estimation," Electronic Components Technology Conference (ECTC 2016), Las Vegas, NV, USA, May 31- June 3, 2016.
  50. C. C. Chang, H. T. Yang, Y. F. Su, Y. T. Hong, and K. N. Chiang, "A Method to Compensate Packaging Effects on three-axis MEMS Accelerometer," ITherm 2016, Las Vegas, NV, USA, May 31- June 3, 2016.
  51. L. L. Liao, C. K. Liu and K. N. Chiang, "Power cycling test and failure mode analysis of high-power module," ICEP2016, Sapporo, Japan, April 20-22, 2016.
  52. M. H. Hsu and K. N. Chiang, "Investigation of thermal cycling maximum temperature effect on fatigue life of WLCSP," ICEP2016, Sapporo, Japan, April 20-22, 2016.
  53. C. J. Chan, F. M. Hsu, Y. F. Su and K. N. Chiang, "Study on current and junction temperature stress aging effect for accelerated aging test of Light emitting diodes," ICEP2016, Sapporo, Japan, April 20-22, 2016.
  54. C.H. Lee, K.C. Wu and K. N. Chiang,"Creep effect on life prediction of WLCSP under different ramp rate of thermal cycling", MAM 2015, Greboble, France, May 18-21, 2015.
  55. H. C. Huang, L. L. Liao, T. Y. Hung, K. H. Liao, C. C. Wang and K. N. Chiang,"Reliability assessment on the temperature profiles effect of the power module", MAM 2015, Greboble, France, May 18-21, 2015.
  56. L. L. Liao, T. Y. Hung, C. K. Liu, Y. F. Su and K. N. Chiang, "Study on configuration design of interconnection in high power module" EuroSimE 2015, Budapest, Hungary, April 20-22, 2015.
  57. H. T. Yang, Y. F. Su and K. N. Chiang, "Research on Packing Effects of Three-axis SOI MEMS Accelerometer" EuroSimE 2015, Budapest, Hungary, April 20-22, 2015.
  58. F. M. Hsu, Y. F. Su and K. N. Chiang, "Determination of the Junction Temperature of Gallium Nitride (GaN)-based High Power LED Under Thermal with Current loading Conditions" ICEP2015, Kyoto, Japan, April 15-17 .
  59. C. C. Yang, C. C. Tsai, Y. F. Su and K. N. Chiang, "Analysis of LED Wire Bonding Process Using Arbitrary Lagrangian -Eulerian and Equilibrium Mesh Smoothing Algorithm" ICEP2015, Kyoto, Japan, April 15-17 .
  60. K. C. Wu, S. Y. Lin and K. N. Chiang, "Investigation of Strain Rate Effect on Lifetime Performance of Wafer Level CSP Under Different Thermal Cycling Loading Rate," IMPACT 2014, Taipei, Taiwan, October 22-24.
  61. W. J. Lee, J. G. Chang, K. N. Chiang, A. V. Bolesta, V. A. Lebiga and V. M. Gomin, "Thermal Stability of Graphene Sheet on the Si Surface under Thermal Processing: A Molecular Dynamics Study" International Conference on the Methods of Aerophysical Research, Novosibrisk, Russia, June 30 - July 6, 2014.
  62. K. C. Wu, and K. N. Chiang, “Investigation of solder creep behavior on wafer level CSP under thermal cycling loading,” Electronics Packaging (ICEP), 2014 International Conference on, Toyama, Japan, 23-25 April, 2014.
  63. F. M. Hsu and K. N. Chiang, “Thermal Analysis and Reliability Assessment of Power Module under Power Cycling Test Using Global- Local Finite Element Method”, Electronics Packaging (ICEP), 2014 International Conference on, Toyama, Japan, 23-25 April, 2014.
  64. T. L. Chou, C. C. Lee, H. N. Chiang, C. T. Lin, Y. F. Su, and K. N. Chiang, "Study on Thermal Induced Stress Hysteresis Behavior of Thin Film Sensor," ThinFilms 2014, Chongqing, China, Jul. 15-18, 2014.
  65. H. J. Wang, H. A. Deng, S. Y. Chiang, Y. F. Su, and K. N. Chiang, "Development of a Feasible Simulation Methodology for Residual Stress Assessment of Multilayer Thin Film Structure," ThinFilms 2014, Chongqing, China, Jul. 15-18, 2014.
  66. Y. H. Yang, Y. F. Su, and K. N. Chiang, "Acceleration Factor Analysis of Aging Test on Gallium Nitride (GaN)-based High Power Light-emitting Diode (LED)," ITherm 2014, Orlando, USA, May 27-30, 2014.
  67. Y. F. Su, C. T. Lin, T. Y. Kuo, and K. N. Chiang, "Structure design and reliability assessment of double-sided with double-chip stacking packaging," EuroSimE 2014, Gent, Belgien, April 7-9, 2014.
  68. L.L. Liao, T. Y. Hung, C. K. Liua, Y. F. Su, and K. N. Chiang, "Study on configuration design of interconnection in high power module," EuroSimE 2014, Gent, Belgien, April 7-9, 2014.
  69. H. C. Chen, Y. C. Chiang, T. Y. Hung, K. N. Chiang, "Investigating the Temperature Effect of Reliability on Integration IC 3D Packaging under Drop Test", Publishes at the 15th Electronics Packaging Technology Conference, Dec. 11-13, 2013, Singapore.
  70. H. C. Huang, T. Y. Hung, S. Y. Lin, K. H. Liao, C. C. Wang, K. N. Chiang, "Reliability Assessment of the Temperature Profiles Effect on the Power Module", Published at The 29th National Conference on Theoretical and Applied Mechanics & The 1st International Conference on Mechanics, Nov 8-9, 2013, Hsinchu, Taiwan.
  71. K. C. Lin, C.C. Tsai, Y. F. Su, T. Y. Hung, K. N. Chiang, "Analysis of LED Wire Bonding Process Using Arbitrary Lagrangian-Eulerian and Explicit Time Integration Methods", IMPACT2013, Taipei,Taiwan, Oct 23-25, 2013.
  72. Y. F. Su, C. T. Lin, T. Y. Kuo, and K. N. Chiang, "Development of Double-Sided with Double-Chip Stacking Structure using Panel Level Embedded Wafer Level Packaging," Electronic Components Technology Conference (ECTC 2013), Las Vegas, NV, USA, May 28-31, 2013.
  73. C. J. Huang, T. Y. Hung and K. N. Chiang, "The Mechanical Properties of Carbon Nanotubes Ropes Using Atomistic-Continuum Mechanics and the Equivalent Methods", ICCES 2013, May 24-28, Seattle, USA.
  74. T. Y. Hung, C. C. Wang, and K. N. Chiang, "Bonding Wire Life Prediction Model of the Power Module under Power Cycling Test," EuroSIME 2013, Wroclaw, Poland, April 15-17, 2013.
  75. H. C. Huang, T. Y. Hung, C. C. Wang, K. C. Lu, and K. N. Chiang, "The Solder Creep Behavior of Power Module Subject to Temeperature Cycling Test with Different Temperature Profiles," ICEP2013, Osaka, Japan, April 10-12, 2013.
  76. L. L. Liao, T. Y. Huang, C. K. Liu, W. Li, M. J. Dai, and K. N. Chiang, "Electro-thermal finite element analysis and verification of power module with aluminum wire", Materials for Advanced Metallization Conference, MAM 2013, Leuven, Belgium, Mar. 10-13, 2013.
  77. L. L. Liao, M. J. Dai, C. K. Liu, and K. N. Chiang, "Thermo-electric finite element analysis and characteristic of thermoelectric generator with intermetallic compound", Materials for Advanced Metallization Conference, MAM 2013, Leuven, Belgium, Mar. 10-13, 2013, 2013.
  78. C. F. Huang, Y. F. Su, C. B. Lin, and K. N. Chiang, "Research on the degradation of AlGaInP Ultra High Brightness LEDs influenced by ohmic metal design", Materials for Advanced Metallization Conference, MAM 2013, Leuven, Belgium, Mar. 10-13, 2013.
  79. Y. F. Su, Y. H. Yang, W. K. Yang, and K. N. Chiang, "A Thermal Performance Assessment of Panel Type Packaging(PTP) Technology for High Efficiency LED," 14th International Conference on Electronics Materials and Packaging, December 13-16, 2012, Hong Kong.
  80. Y. J. Lee, Y. F. Su, T. Y. Hung, and K. N. Chiang, "Reliability Analysis of 3D IC Integration packaging under Drop Test Condition," IMPACT 2012, Taipei, Taiwan, October 24-26.
  81. C. C. Lee, Y. F. Su, C. S. Wu, and K. N. Chiang, "Investigation of Interconnect Design on Interfacial Cracking Energy of Al/TiN Barriers under a Flexural Load," ThinFilms2012, Singapore, July 14-17.
  82. C. F. Huang, Y. F. Su, S. Y. Yang, C. L. Hsu, N. C. Chen, and K. N. Chiang, "Quantum Efficiency Investigation at high Current Density of Ultra-High-Brightness LEDs," ITHERM 2012, San Diego, California, USA, May 30 - June 1.
  83. H. H. Chang, L. L. Liao and K. N. Chiang, " External Stress Effect to Electromigration on Thermal Annealed and Residual Stress Controlled Aluminum Strip," ICEP2012, Tokyo, Japan, April 17-21.
  84. L. L. Liao, M. J. Dai, C. K. Liu, J. Y. Chang and K. N. Chiang, " Development and analysis of the thermoelectric material with intermetallic compound," ICEP 2012, Tokyo, Japan, April 17-21.
  85. C. T. Lai, T. Y. Hung, and K. N. Chiang, "Investigation on the Effect of Surface Roughness on the Fracture Strength of SCS," EuroSimE 2012, Lisbon, Portugal, April 16-18.
  86. H. H. Chang, T. Y. Hung, and K. N. Chiang, "Residual Stress Effect of Electromigration Behavior on Aluminum Strip," Materials for Advanced Metallization Conference, MAM 2012, Grenoble, France, Mar. 11-14, 2012.
  87. T. Y. Hung, C. J. Huang, C. C. Lee, C. C. Wang, K. C. Lu, and K. N. Chiang, "Thermal Cycling Period Effect of Fatigue Life of the Power Module," Materials for Advanced Metallization Conference, MAM 2012, Grenoble, France, Mar. 11-14, 2012.
  88. C. J. Huang, T. Y. Hung, K. N. Chiang, "Analysis of the Mechanical Properties of Si/SiGe Heterostructure using Atomistic-continuum Mechanics with Constraint Equations,"APMC-10, ICONN 2012 & ACMM-22, Perth, WA Australia Feb. 5-9, 2012.
  89. T. Y. Hung, S. Y. Chiang, C. J. Huang, C. C. Wang, K. C. Lu, and K. N. Chiang, "Dwell Time Effect and Thermal Fatigue Life Assessment of Power Module," 13th International Conference on Electronics Materials and Packaging, 3 pp. Kyoto, Japan, 2011.
  90. T. H. Kuo, Y. F. Su, C. J. Wu, and K. N. Chiang, "Stress/Stain Assessment and Reliability Prediction of Through Silicon Via and Trace Line Structures of 3D Packaging," EuroSimE2011, Linz, Austria, April 18-20, 2011.
  91. T. L. Chou, S. Y. Yang, C. J. Wu, C. N. Han, and K. N. Chiang, “Measurement and simulation of interfacial adhesion strength between SiO2 thin film and III-V material,” ESREF 2011, Bordeaux, France, Oct. 3-7, 2011.
  92. P. C. Chen, Y. F. Su, S. Y. Yang, and K. N. Chiang, "Determination of Silicon Die Initial Crack Using Acoustic Emission Technique," IMPACT 2011, Taipei, Taiwan, October 19-21, 2011.
  93. W. L. Tsai, H. H. Chang, C. H. Chien, J. H. Lau, H. C. Fu, C. W. Chiang, T. Y. Kuo, Y. H. Chen, R. Lo and M. J. Kao, “How to Select Adhesive Materials for Temporary Bonding and De-Bonding of 200mm and 300mm Thin-Wafer Handling for 3D IC Integration?,” in Electronic Components and Technology Conference, May 31-Jun. 3, Florida, US, 2011.
  94. H. H. Chang, J. H. Huang, C. W. Chiang, Z. C. Hsiao, H. C. Fu, C. H. Chien, Y. H. Chen, W. C. Lo, and K. N. Chiang, “Process Integration and Reliability Test for 3D Chip Stacking with Thin Wafer Handling Technology,” in Electronic Components and Technology Conference, May 31-Jun. 3, Florida, US, 2011.
  95. T. Y. Hung, S. Y. Chiang, C. J. Huang, C. C. Lee, K. N. Chiang, "Thermal-mechanical behavior of the bonding wire for a power module subjected to the power cycling test," 22nd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), October 3-7, 2011, Bordeaux, France.
  96. H. J.Wang, H.A.Deng, S. Y. Chiang, and K. N. Chiang "Thin Film ResidualStress Assessment of Capacitive MEMS Microphones Using Process ModelingTechnology," InterPACK 2011, Portland, Oregon, USA, Jul 6-8, 2011.
  97. P. C. Chen, S. Y. Yang, K. N. Chiang "Determination and Verification of Silicon Die Strength Using Ball-Breaker Test," InterPACK 2011, Portland,Oregon, USA, Jul 6-8, 2011.
  98. S.Y. Chiang, T.Y. Hung, H.C. Ou, and K.N. Chiang, "Electro-Thermal Analysis of the Insulated Gate Bipolar Transistor Module Subjected to Power Cycling Test Using Specified Boundary Condition Technology," EuroSimE 2011, Linz, Austria, April 18-20, 2011.
  99. C. J. Huang, C.J. Wu, H.A. Teng, and K.N. Chiang, "Research on Multi-Scale Structural Analysis using the Atomistic-Continuum Equivalent Mechanics," CSWNST-8, Hong Kong, Dec. 19-22, 2010.
  100. S. Y. Syu, T. Y. Hung, C. J. Huang, H. J. Wang, H. L. Lee and K.N. Chiang, "Reliability Assessment of 3D Chip Stacking Package Using Metal Bonding and Through Silicon Via Technologies," ASME International Mechanical Engineering Congress & Exposition (IMECE), Vancouver, Canada, Nov. 12-18, 2010.
  101. C. J. Huang, C.J. Wu, H.A. Teng, and K.N. Chiang, "Carbon Nanotubes Structural Mechanics Using the Atomistic-Continuum Mechanics and Equivalent Methods," ACCM-7, Taipei, Taiwan, Nov. 15-18, 2010.
  102. S. Y. Yang, T. L. Chou, C. F. Huang, C. J. Wu, C. L. Hsu, and K. N. Chiang "Strength Determination of Light-emitting diodes and Chip Structure Design," IMPACT2010, Taipei, Taiwan, Oct 20-22, 2010.
  103. N. Y. Wang, S. Y. Chiang, T. L. Chou and K. N. Chiang, "Life Prediction of High Concentration Photovoltaic Modules Subjected to Thermal Cycling Test," IMPACT2010, Taipei, Taiwan, Oct. 20-22.
  104. S. Y. Yang, T. L. Chou, C. F. Huang, C. J. Wu, C. L. Hsu, and K. N. Chiang "Determination of Maximum Strength and Optimization of LED Chip Structure," ESTC2010, Berlin, Germany, Sep 14-16, 2010.
  105. Yen-Fu Su, Tuan-Yu Hung, Shin-Yueh Yang, and Kuo-Ning Chiang, "A Study on the Thermal Performance of a Chip-in-substrate-type LED Package Structure" ICSJ2010, Tokyo, Japan, August 24-26, 2010.
  106. Ning-Yuan Wang, Shih-Ying Chiang, Tsung-Lin Chou, Zun-Hao Shih, Hwen-Fen Hong and Kuo-Ning Chiang, "Transient Thermal Analysis of High-Concentration Photovoltaic Cell Module Subjected to Coupled Thermal and Power Cycling Test Conditions," Itherm2010, Las Vegas, Nevada, USA, June 2-5, 2010.
  107. T. Y. Hung, S. Y. Chiang, C. Y. Chou, C. C. Chiu, and K. N. Chiang, "Thermal Design and Transient Analysis of Insulated Gate Bipolar Transistors of Power Module," ITherm 2010, Las Vegas, USA, June 2-5, 2010.
  108. C. J. Wu, M. C. Hsieh, and K. N. Chiang, "Delamination Investigation of Copper Bumps in 3D Chip Stacking Packages Using the Modified Virtual Crack Closure Technique," ICEP 2010, Sapporo, Japan, May 12-14, 2010.
  109. S. Y. Chiang, T. Y. Hung, Ray Hsing and K. N. Chiang, "Temperature Dependent Current Crowding Analysis of Insulated Gate Bipolar Transistor," ICEP2010, Sapporo, Hokkaido, Japan, May 12-14, 2010.
  110. H. H. Chang, J. H. Huang, C. W. Chiang, Z. C. Hsiao, H. C. Fu, Y. H. Chen and K. N. Chiang, “Process Integration for 3D Chip Stacking with Thin Wafer Handling Technology,” in Materials for Advanced Metallization Conference, Mar. 7-10, Mechelen, Belgium, 2010.
  111. Y. F. Su, S. Y. Yang, W. H. Chi and K. N. Chiang, "Light Degradation Prediction of High Power Light Emitting Diode Lighting Modules,"EuroSimE2010, Bordeaux, France, Apr. 26-28, 2010.
  112. C. J. Wu, M. C. Hsieh, C. C. Chiu, T. Y. HungM. C. Yew, and K. N. Chiang "Interfacial Delamination Investigation between Copper Bumps in 3D Chip Stacking Package by Using the Modified Virtual Crack Closure Technique," MAM 2010, Mechelen, Belgium, Mar. 7-10, 2010.
  113. Shih-Ying Chiang, Tsung-Lin Chou, Hwen-Fen Hong and Kou-Ning Chiang, "Life Prediction of HCPV Under Thermal Cycling Test Condition," MAM2010, Mechelen, Belgium, Mar 7-10, 2010.
  114. Chao-Jen Huang, Chung-Jung Wu, Hung-An Teng, and Kuo-Ning Chiang "A Robust Nano-Mechanics Approach for Tensile and Modal Analysis Using Atomistic-Continuum Mechanics Method," ICONN 2010, Sydney, Australia, Feb 22-26, 2010
  115. Tsung-Lin Chou, Shin-Yueh Yang, and Kuo-Ning Chiang, “Overview and Applicability of Residual Stress Estimation of Film-Substrate Structure,” International Conference of Advanced Manufacturing, Feburary 2-5, 2010, Kenting, Taiwan.
  116. H. A. Deng, S. Y. Yang, C. N. Han, T. L. Chou, and K. N. Chiang "Warpage Analysis of High Power InGaN Light Emitting Diodes after Laser Lift-off," EMAP 2009, Penang, Malaysia, Dec 1-3, 2009.
  117. S. Y. Chiang, T. L. Chou, Z. H. Shih, H. F. Hong and K. N. Chiang "Non-Uniform Thickness Effect of Die Bonding Interface in High-Concentration Photovoltaic Module," EMAP 2009, Penang, Malaysia, Dec 1-3, 2009.
  118. C. Y. Chou, C. J. Huang, M. Sano, and K. N. Chiang, "Metal trace impact life prediction model for stress buffer enhanced package," 17th European Microelectronics and Packaging Conference & Exhibition (EMPC2009), Rimini, Italy, June 15-18, 2009.
  119. T. Y. Hung, M. C. Yew, C. Y. Chou, and K. N. Chiang, "A study of thermal performance for chip-in-substrate package on package," 17th European Microelectronics and Packaging Conference & Exhibition (EMPC2009), Rimini, Italy, June 15-18, 2009.
  120. H. H. Chang, Y. C. Shih, Z. C. Hsiao, C. W. Chiang, Y. H. Chen and K. N. Chiang, "3D Stacked Chip Technology Using Bottom-up Electroplated TSVs",Electronic Components and Technology Conference (ECTC 2009), San Diego, California USA, May 26-29, 2009.
  121. Masafumi Sano, Chan-Yen Chou, Tuan-Yu Hung, Shin-Yueh Yang, Kuo-Ning Chiang, “Uncertainty and Reliability Analysis of Chip Scale Package Subjected to Board-level Drop Test”, International Conference on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE2009), Delft, Netherlands April 27-29, 2009.
  122. C. J. Huang, C. Y. Chou, K. N. Chiang, “Dynamic Study and Structure Enhancement of Small Outline Dual-in-line Memory Module”, International Conference on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE2009), Delft, Netherlands April 27-29, 2009.
  123. W. H. Chi, T. L. Chou, C. N. Han, S. Y. Yang, and K. N. Chiang, "Analysis of Thermal Performance for High Power Light Emitting Diodes Lighting Module", International Conference on Electronics Packaging (ICEP 2009),Kyoto, Japan, April 14-16, 2009.
  124. C. J. Wu, M. C. Hsieh, and K. N. Chiang, "Die-Cracking Evaluation of Silicon Chip Covered with Polymer Film for 3D Chip Stacking Packages," International Conference on Electronics Packaging, ICEP 2009, Kyoto, Japan, Apr. 14-16, 2009.
  125. C. J. Wu, M. C. Hsieh, and K. N. Chiang, "Strength Evaluation of Silicon Die for 3D Chip Stacking Packages Using ABF as Dielectric and Barrier Layer in Through-Silicon Via,", Materials for Advanced Metallization Conference (MAM 2009), Grenoble, France, Mar. 8-11, 2009.
  126. C. C. Chiu, C. J. Huang, S. Y. Yang, C. C. Lee, and K. N. Chiang, "Investigation of the Delamination Mechanism of the Thin Film Dielectric Structure in Flip Chip Packages" Materials for Advanced Metallization Conference (MAM 2009), Grenoble, France, Mar. 8-11, 2009.
  127. Wei-Hao Chi, Tsung-Lin Chou, Cheng-Nan Han, and Kuo-Ning Chiang, "Analysis of Thermal Performance of High Power Light Emitting Diodes Package," 10th Electronics Packaging Technology Conference, Singapore, December, 2008.
  128. Tuan-Yu Hung, Chan-Yen Chou, Ming-Chih Yew and Kuo-Ning Chiang, “Validation and reliability assessment of board level drop test of chip-scale-packaging,” The International Conference on Experimental Mechanics 2008 (ICEM2008), Nanjing, China, November 8-11, 2008.
  129. Ming-Chih Yew, Chun-Fai Yu, Mars Tsai, Dyi-Chung Hu, Wen-Kung Yang, and Kuo-Ning Chiang, "Reliability Analysis of the Panel Base Package (PBPTM) Technology with Enhanced Cover Layer," Proceedings of the 3rd International Microsystems, Packaging, Assembly and Circuits Technology (IMPACT) Conference and the 10th International Conference on Electronics Materials and Packaging (EMAP), pp. 384-387, October 22-24, 2008, Taipei, Taiwan. (Best Student Paper Award).
  130. C. Y. Chou, T. Y. Hung, M. Sano, S. Y. Yang, and K. N. Chiang, "Investigation of influences of PCB on board-level drop test by dynamic simulation and modal analysis," 3rd IMPACT, Oct. 22-24, Taipei, Taiwan.
  131. C. Y. Chou, T. Y. Hung, S. Y. Yang, M. C. Yew, W. K. Yang, and K. N. Chiang, "Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact," ESREF2008, 30 Sep. - 03 Oct., Maastricht, Netherland.
  132. H. P. Wei, M. C. Yew, C. J. Wu, and K. N. Chiang, "Reliability and Thermal Assessment of Stacked Chip-on-Metal Panel Based Package (PBPTM) with Fan-Out Capability," ESTC 2008, 01-04 September, London, England.
  133. T. L. Chou, Z. H. Shih, H. F. Hong, C. N. Han, K. N. Chiang‚ “Investigation of Thermal Performance of High-Concentration Photovoltaic Solar Cell System,” 23rd European Photovoltaic Solar Energy Conference and Exhibition (EU PVSEC), Sep. 1-5, 2008, Valencia, Spain.
  134. H. H. Chang, Y. C. Shih, C. K. Hsu, Z. C. Hsiao, C. W. Chiang, Y. H. Chen, and K. N. Chiang, “TSV Process Using Bottom-up Cu Electroplating and its Reliability Test,” in Electronics System-Integration Technology Conference, September 1-4, Greenwich, UK, 2008.
  135. S. Y. Chiang, S. Y. Yang, C. Y. Chou, M. C. Yew, and K. N. Chiang, "Reliability Analysis of Copper Interconnections of System-in-Packaging Structure using Finite Element Method," ICEPT-HDP2008, 28-31 July, Shanghai, China.
  136. Ming-Chih Yew, Chun-Fai Yu, Mars Tsai, Dyi-Chung Hu, Wen-Kung Yang, and Kuo-Ning Chiang, "A Study of Thermal Performance for the Panel Base Package (PBPTM) Technology, " Proceedings of International Conference on Electronic Packaging Technology and International Symposium on High Density Packaging, ICEPT-HDP 2008, July 28-31, 2008, Shanghai, China.
  137. Ming-Chih Yew, Chung-Jung Wu and Kuo-Ning Chiang, "Trace Line Failure Analysis and Characterization of the Panel Base Package (PBPTM) Technology with Fan-Out Capability," Proceedings of the 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITherm 2008, pp. 862-869, May 28 -31, 2008, Florida, USA.
  138. C. N. Han, T. L. Chou, C. F. Huang, and K. N. Chiang, "Sappire-removed induced the deformation of high power InGaN light emitting diodes," EuroSimE2008, 20-23 April, Freiburg imBreisgau, Germany.
  139. C. Y. Chou, T. Y. Hung, M. C. Yew, W. K. Yang, D. C. Hu, M. C. Tsai, C. S. Huang, and K. N. Chiang, "Investigation of Stress-buffer-enhanced Package Subjected to Board-level Drop Test," EuroSimE2008, 20-23 April, Freiburg im Breisgau, Germany.
  140. C. J. Wu, C. Y. Chou, C. N. Han, and K. N. Chiang, "Estimation and Validation of Elastic Modulus of Carbon Nanotubes Using Nano-Scale Tensile and Vibrational Analysis.", International Conference on Computational & Experimental Engineering and Sciences 2008 (ICCES'08), 16-21 March, 2008, Honolulu, Hawaii, USA.
  141. C.C. Chiu, C.C. Lee, T. L. Chou, C. C. Hsia, K.N. Chiang, “Analysis of Cu/Low-k Structure under Back End of Line Process,” Materials for Advanced Metallization Conference 2008 (MAM2008), March 2-5, 2008, Dresden, Germany.
  142. C. C. Lee, T.L. Chou, C.C. Chiu, C.C. Hsia, K.N. Chiang, “Cracking energy estimation of ultra low-k package using novel prediction approach combined with global-local modeling technique,” Materials for Advanced Metallization Conference 2008 (MAM2008), March 2-5, 2008, Dresden, Germany.
  143. T. L. Chou, Z. H. Shih, H. F. Hong, C. N. Han, K. N. Chiang‚ “Investigation of Thermal Performance of High-Concentration Photovoltaic Solar Cell Package,” International Conference on Electronics Materials and Packaging (EMAP2007), November 19-22, 2007, Daejeon, Korea.
  144. S. Y. Chiang, C. Y. Chou, M. C. Yew, and K. N. Chiang, "Reliability Analysis of Copper Interconnection in System-in-package Structure," International Conference on Electronics Materials and Packaging (EMAP2007), November 19-22, 2007, Daejeon, Korea.
  145. C. J. Huang, C. Y. Chou, C. J Wu, and K. N. Chiang, "Investigation of the mechanical properties of nano-scale metallic crystal structural with point defects," European Nano System 2007 (ENS'07), December 3-4, 2007, Paris, France.
  146. Ming-Chih Yew and Kuo-Ning Chiang, "A Study of Material Effects for the Panel Level Package (PLP) Technology," Proceedings of the 2nd International Microsystems, Packaging, Assembly and Circuits Technology conference, IMPACT2007, pp. 98-101, October 1-3, 2007, Taipei, Taiwan.
  147. H. N. Chiang, T. L. Chou, C. T. Lin, K. N. Chiang‚“Investigation of the Hysteresis Phenomenon of A Silicon-based Piezoresistive Pressure Sensor,” International Microsystems, Packaging, Assembly and Circuits Technology conference, Taipei, Taiwan, 2007.
  148. C. C. Chiu , C. C. Lee and K.N. Chiang, "Study of Lamina Fracture of Cu/Low-k Interconnects Using the J-Integral Method," The 7th International Conference on Fracture and Strength of Solids (FEOFS 2007) 27-30 August 2007, Urumqi, CHINA.
  149. H. P. Wei, M. C. Yew, C. J. Huang, and K. N. Chiang, "Failure mode and thermal performance analysis of stacked panel level package (PLP)," InterPACK 2007, July 8-12, 2007, Vancouver, BC, Canada.
  150. C. Y. Chou, C. J. Wu, H. P. Wei, M. C. Yew, C. C. Chiu, and K. N. Chiang, "Thermal management on hot spot elimination / junction temperature reduction for high power density system in package structure," InterPACK 2007, July 8-12, 2007, Vancouver, BC, Canada.
  151. Chan-Yen Chou, Chung-Jung Wu, Hsiu-Ping Wei, Ming-Chih Yew, Chien-Chia Chiu and Kuo-Ning Chiang, "Thermal Management on Hot Spot Elimination / Junction Temperature Reduction for High Power Density RF Multi-chip Module," Thermal Stress 2007, June 4-7, 2007, Taipei, Taiwan.
  152. C. N. Han, C. Y. Chou, and K. N. Chiang, "Investigation of Mechanical Strength of The Nanoshell of Bacteriophage Phi-29," NSTI Nanotech2007, May20-24, 2007, Santa Clara, USA.
  153. C. N. Han, C. Y. Chou, and K. N. Chiang, "Investigation of dsDNA Molecule Mechanical Behavior Using Atomistic Continuum Mechanics Method," NSTI Nanotech2007, May20-24, 2007, Santa Clara, USA.
  154. C. J. Wu, C. Y. Chou, C. N. Han, and K. N. Chiang, "Simulation and Validation of CNT Mechanical Properties – The Future Interconnection Material.", Electronic Components and Technology Conference (ECTC 2007), May 30 - Jun. 1, Reno, USA.
  155. Chun-Te Lin, Chan-Yen Chou, and Kuo Ning Chiang, "Estimation and validation of mechanical properties of single crystal silicon by atomic-level numerical model," International Conference on Experimental Mechanics (ICEM13), Alexandroupolis, Greece, July1-6, 2007.
  156. Ming-Chih Yew, Hsiu-Ping Wei, Ching-Shun Huang, Dyi-Chung Hu, Wen-Kung Yang and Kuo-Ning Chiang, "A Study of Failure Mechanism and Reliability Assessment for the Panel Level Package (PLP) Technology," Proceedings of 8th International conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSIME2007, April 16-18, 2007, London, England.
  157. Hsiu-Ping Wei, Ming-Chih Yew, Wen-Kung Yang, and Kuo-Ning Chiang, "Reliability Analysis of a Package-on-Package Structure using the Novel WLCSP Technology with Fan-Out Capability," The 8th International Conference on Electronics Materials and Packaging, EMAP 2006, 11-14 December 2006, Hong Kong.
  158. Chun-Te Lin, Chan-Yen Chou, Chao-Jen Huang, and Kuo-Ning Chiang, "Validation of mechanical properties of the nanoscale single crystal IV-A group material by Atomistic-Continuum Mechanics Model," The 30th Conference of Theoretical and Applied Mechanics, 15-16 December 2006 , Taiwan.
  159. C. T. Lin and K. N. Chiang, "From Atomic-Level Lattice Structure to Estimate the Silicon Mechanical Bulk Behavior Using the Atomistic-Continuum Mechanics," 5th ACCM, Nov. 27-30, 2006, HongKong, Hong Kong SAR.
  160. C. T. Lin and K. N. Chiang, "From Atomic-Level Lattice Structure to Estimate the Silicon Mechanical Bulk Behavior Using the Atomistic-Continuum Mechanics," 5th ACCM, Nov. 27-30, 2006, HongKong, Hong Kong SAR.
  161. Chung-Jung Wu, Chan-Yen Chou, Cheng-Nan Han, Kuo-Ning Chiang, "Numerical Simulation of the Mechanical Properties of Carbon Nanotube Using the Atomistic-Continuum Mechanics.", European Nano System 2006, 14-15 December 2006, Paris, France.
  162. Chien Chen Lee, Chang Chun Lee, Chien Chia Chiu, Kuo Ming Chen, Frank Kuo and Kou Ning Chiang, "Electromigration Characteristic of SnAg3.0Cu0.5 Flip-Chip Interconnection," 56th Electronic Components and Technology Conference (ECTC), May 30 - June 2, 2006 in San Diego, CA, USA.
  163. Chang-Chun Lee, Chien-Chia Chiu, Kuo-Ning Chiang, "STABILITY OF J-INTEGRAL CALCULATION IN THE CRACK GROWTH OF COPPER/LOW-K STACKED STRUCTURES," ITherm 2006, May 30 - June 2, 2006 in San Diego, CA, USA.
  164. M. C. Yew, C. Yuan, C. N. Han, C. S. Huang, W. K. Yang, K.N. Chiang, "Factorial Analysis of Chip-on-Metal WLCSP Technology with Fan-Out Capability," Proceedings of the 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA2006, July 3-7, 2006, Singapore, pp. 223-228.
  165. Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Kuo-Ning Chiang, Terry Ku and Kenny Cheng, "LEAD-FREE FLIP CHIP PACKAGE RELIABILITY AND THE FINITE ELEMENT-FACTORIAL DESIGN METHODOLOGY," Proceedings of the IMAPS-Taiwan 2006 Technical Symposium, June 28 - July 1, 2006, Taipei World Trade Center, Taipei, Taiwan.
  166. Cadmus Yuan, Chan-Yen Chou, Cheng-Nan Han, Ming-Chih Yew and Kou-Ning Chiang,"12" to 8" wafer transformationn technique using novvel glass WLCSP structure," Proceedings of the IMAPS-Taiwan 2006 Technical Symposium, June 28 - July 1, 2006, Taipei World Trade Center, Taipei, Taiwan.
  167. Ming-Chih Yew, Ching-Shun Huang, Wen-Kung Yang and Kou-Ning Chiang,"Reliability and Characterization of Novel WLCSP with Fan-Out Capability," Proceedings of the IMAPS-Taiwan 2006 Technical Symposium, June 28 - July 1, 2006, Taipei World Trade Center, Taipei, Taiwan.
  168. Ming-Chih Yew, Yu- Hua Chen, Wen-Kung Yang, Kuo-Ning Chiang,"Using FEM-based Method for Sensitivity Design of Chip-in-Substrate-Package," Proceedings of the IMAPS-Taiwan 2006 Technical Symposium, June 28 - July 1, 2006, Taipei World Trade Center, Taipei, Taiwan.
  169. C. Yuan, G. Q. Zhang, C. S. Huang, C. H. Yu, C. C. Yang, W. K. Yang, M. C. Yew, C. Y. Chou and K. N. Chiang, "Design, Experiment and Analysis of the Solder on Rubber (SOR) structure of WLCSP," Proceedings of the 7th International conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSIME2006, Como (Milano), Italy, April 23 - 26, 2006, pp. 619-625.
  170. C. Yuan, G. Q. Zhang, C. S. Huang, C. H. Yu, C. C. Yang, W. K. Yang, M. C. Yew, C. N. Han and K. N. Chiang, "Design and Analysis of a novel fan-out WLCSP structure," A Proceedings of the 7th International conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSIME2006, Como (Milano), Italy, April 23 - 26, 2006, pp. 297-304.
  171. Liu, C. M., Lee, C. C., Ku, H. T., Chiu, C. C., and Chiang, K. N., 2006, “Interconnect Design and Thermal Stress/Strain Analysis of Flip Chip Packaging,” International Conference on Experimental Mechanics 2006 (ICEM 2006), Sep. 26-29, Jeju, Korea.
  172. Lee, C. C., Ku, H. T., Chiu, C. C., and Chiang, K. N., 2006, “A Novel Prediction Technique for Interfacial Crack Growth of Electronic Interconnect,” International Conference on Experimental Mechanics 2006 (ICEM 2006), Sep. 26-29, Jeju, Korea.
  173. C. H. Chu, C. T. Lin, T. L. Chou, K. N. Chiang, “Investigation of packaging effect of silicon-based piezoresistive pressure sensor,” 2006 ASME International Mechanical Engineering Congress and Exposition, IMECE2006, Nov. 5-10, 2006.
  174. Chung-Jung Wu, Chan-Yen Chou, Cheng-Nan Han, Kuo-Ning Chiang, “Investigation of Carbon Nanotube Mechanical Properties Using The Atomistic-Continuum Mechanics Method.”, NSTI Nanotech 2006, Boston, Massachusetts ( USA), 2006.
  175. C. N. Han, C. Y. Chou, C. J. Wu and K. N. Chiang, “Investigation of ssDNA Backbone Molecule Mechanical Behavior Using Atomistic-Continuum Mechanics Method”, NSTI 2006 Nanotechnology Conference, May 7-11, 2006, Boston, Massachusetts, U.S.A.
  176. Ming-Chih Yew, Chang-Ann Yuan, Yu- Hua Chen, Wen-Kung Yang, Kuo-Ning Chiang, "Sensitivity Design of Chip-in-Substrate-Package Using DOE with Factorial Analysis Technology," EuroSIME2006 International Conference, April 23-April 26, 2006, Como (Milano), Italy.
  177. Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Chan-Yen Chou and Kuo-Ning Chiang , "Reliability Impact of Highly Temperature-Dependent Underfill Material to the Lead-Free Flip Chip Package," EuroSIME2006 International Conference, 2006,in Como (Milano), Italy.
  178. Kuo-Ming Chen, J. D. Wu, Kuo-Ning Chiang “Effect of pre-bump probing and bumping processes on eutectic solder bump electromigration” Science Direct, 28 February 2006.
  179. Chan-Yen Chou, Cadmus Yuan, Chung-Jung Wu and Kuo -Ning Chiang, "Numerical Simulation of the Mechanical Properties of Nanoscale Metal Clusters Using the Atomistic-Continuum Mechanics Method.", European Nano System 2005, 14-16 December 2005, Paris, France.
  180. C. Yuan, C. N. Han, C. Y. Chou, M. C. Yew and K. N. Chiang, "Simulation of unzipping dsDNA mechanical response using Clustered Atomistic-Continuum Method." ICCES'05 International Conference, Dec. 1-6, 2005, in Chennai, India.
  181. C. N. Han, C. Yuan and K. N. Chiang, "Investigation of ssDNA molecule using clustered atomistic method and its application to the dsDNA analysis," published at Microelectronics, MEMS, and Nanotechnology 2005 (SPIE), Brisbane, Australia, Dec. 11–14 2005.
  182. C. H. Chang, C. Y. Chou, C. N. Han, C. T. Peng, K. N. Chiang, "Local-Strain Effect of the SiNx/Si Stacking and Nano-Scale Triple Gate Si/SiGe MOS Transistor", published at Microelectronics, MEMS, and Nanotechnology 2005 (SPIE), Brisbane, Australia, Dec. 11–14 2005.
  183. Cadmus Yuan, C. Y. Chou, C. N. Han, and K. N. Chiang, "Design and Analysis of Novel Glass WLCSP Structure.", Published at The 29th National Conference on Theoretical and Applied Mechanics, Dec. 16-17, 2005, Hsinchu, Taiwan, R.O.C.
  184. H. T. Ku and K. N. Chiang, "STRESS INDUCED VARIATION OF ELECTRICAL CHARACTERISTICS OF ANALOG DEVICES", Published at The 29th National Conference on Theoretical and Applied Mechanics, Dec. 16-17, 2005, Hsinchu, Taiwan, R.O.C.
  185. Chien Chen Lee, Kuo Ming Chen, Frank Kuo, and Kou Ning Chiang, “Thermo-electromigration Study of Lead-free Solder Bumps”, The 2006 Pan Pacific Microelectronics Symposium, Jan. 17-19, 2006, Hawaii, USA.
  186. C. Y. Chou, C. A. Yuan, and K. N. Chiang, "Investigation of Nano-scaled Material Behavior Using Atomistic-Continuum Mechanics Method." The 22nd National Conference on Mechanical Engineering, CSME, Nov. 25-26, C11-006, 2005.
  187. M. C. Yew, C. C. Lee, and K. N. Chiang, "Reliability Analysis of a New Soft Joint Protection Technology Using in WLCSP." Taiwan ANSYS User Conference, 2005 .
  188. Lee, C. C., Liu, C. M., and Chiang, K. N., 2005, “Hybrid Solder Pad System for Enhancing the Reliability of Wafer Level Packaging,” Taiwan ANSYS User Conference, 2005 .
  189. Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Kuo-Ning Chiang, Terry Ku and Kenny Cheng "Reliability Assessment of Lead-Free Flip Chip Package Using Factorial Design Methodology", Taiwan ANSYS User Conference, 2005 .
  190. C. T. Lin and K. N. Chiang,”Investigation of Nano-Scale Single Crystal Silicon Using the Atomistic-Continuum Mechanics with Stillinger-Weber Potential Function,” published at NanoSingapore 2006 (IEEE), Singapore, Jan. 10-13, 2006.
  191. C. T. Lin and K. N. Chiang,” Thermal and Mechanical Responses of Thermomechanical Microprobe for High Density Storage Technology,” published at Microelectronics, MEMS, and Nanotechnology 2005 (SPIE), Brisbane, Australia, Dec. 11–14 2005.
  192. C. A. Yuan, C. N. Han, and K. N. Chiang, “Investigation of Sequence-Dependent dsDNA Mechanical Behavior using Clustered Atomistic-Continuum Method”, published at Nanotech Conference, Anaheim, USA, May. 8-11.
  193. C. H. Chang, C. Y. Chou, C. T. Peng, C. N. Han, K. N. Chiang, “Investigation of Local-Strain Effect of the Nano-Scale Triple Gate Si/SiGe and SiNx/Si Stacking MOS Transistor”, published at Nanotech Conference, Anaheim, USA, May. 8-11.
  194. C. C. Lee, and K. N. Chiang, 2005, “Reliability Analysis of WLCSP Using Tie-Release Crack Prediction Finite Element Technique,” ASME International Mechanical Engineering Congress & Exposition (ASME, EI), Orlando, Florida, USA, Nov. 5-11.
  195. C. C. Lee, C. C. Lee, C. Y. Cheng, and K. N. Chiang, 2005, “Robust Design for the Reliability Optimization of WLCSP Using Response Surface Methodology,” IMAPS-TAIWAN 2005 International Technical Symposium, pp. 209-214, Taipei, Taiwan, Jun. 23-25.
  196. C.C. Lee, S. M. Chang, K. N. Chiang, "Design of Double Layer WLCSP Using DOE with Factorial Analysis Technology.", 6th Electronics Packaging Technology Conference (EPTC 2004)(IEEE, EI), pp. 776-781. Singapore, 2004, Dec. 8-10.
  197. S. M. Chang, C. Y. Cheng, L. C. Shen, K. N. Chiang, Y. J. Hwang, Y. F. Chen, J. D. Ko, H. T. Hu, K. C. Chen, and C. Y. Chang, "A Novel WLCSP Technology with High Reliability, Low Cost and Ease of Fabrication.", 6th Electronics Packaging Technology Conference (EPTC 2004)(IEEE, EI), pp. 7-12. Singapore, 2004, Dec. 8-10.
  198. C. A. Yuan and K. N. Chiang., “Numerical Simulation for B-S Structural Transition of Nicked dsDNA Using Enriched Finite Element Method”, Taiwan International Conference on Nano Science and Technology, June 30-July 3, 2004, HsinChu, Taiwan.
  199. C. A. Yuan, C. N. Han and K. N. Chiang, "Atomistic to Continuum Mechanical Investigation of ssDNA and dsDNA using Transient Finite Element Method," Inter-Pacific Workshop on Nanoscience and Nanotechnology, Nov. 22-Nov. 24, City University of Hong Kong, Hong Kong SAR.
  200. W. C. Liao, C. T. Lin and K. N. Chiang, “Experiment Validation of a Nano-Probe for the AFM based on the Large Deflection Theory,” Published (CD-ROM) at Annual Meeting of CSME, Nov. 11, 2004, KaoHsiung.
  201. C. T. Lin, W. C. Liao, J. Y. Chen, H. C. Su and K. N. Chiang, “Design and Analysis of a Nano-Probe for the AFM based on the Small/Large Deflection Theory,” Published at 2004 ASME Intl. Mechanical Engineering Congress and Exposition, Nov. 13-19, 2004, Anaheim, USA.
  202. C. C. Lee and Kou Ning Chiang, “RF Substrate Via Relative Issue Discussion - Via and Ni/Au Surface Layer Crack,” The 7th VLSI Packaging Workshop of Japan, Nov. 30 – Dec. 2, 2004, Kyoto, Japan.
  203. C. M. Liu, C. C. Lee, and K. N. Chiang, “Solder Joints Layout Design and Reliability Enhancement of Wafer Level Packaging,” 6th IEEE EuroSimE2005 conference (IEEE/EI), pp.234-241, Berlin, Germany, Apr. 18-20, 2005.
  204. C. C. Lee, C. C. Lee and K. N. Chiang, “Thermal Performance and Solder Joint Reliability for Board Level Assembly of Modified Leadframe Module,” 6th IEEE EuroSimE2005 conference (IEEE/EI), pp.553-558, Berlin, Germany, Apr. 18-20, 2005.
  205. C. C. Lee, S. M. Chang and K. N. Chiang, K. N., “Design of Double Layer WLCSP Using DOE with Factorial Analysis Technology,” Published at 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE, EI), December 8-10, 2004, Singapore.
  206. J. Y. Chen, C. T. Lin, W. C. Liao, H. C. Su, C. H. Ysai and K. N. Chiang, “A New Nano-Probe Using Micro Assembly Transfer”, Published at 3rd Cross-Strait Workshop on Nano Science & Technology, April 27 – 29, 2004, HuaLian, Taiwan.
  207. J. Y. Chen, C. T. Lin, W. C. Liao, H. C. Su, C. H. Ysai and K. N. Chiang, “A New Nano-Probe Using Micro Assembly Transfer”, Published at 3rd Cross-Strait Workshop on Nano Science & Technology, April 27 – 29, 2004, HuaLian, Taiwan.
  208. C.H. Chang, C.T. Peng and K.N. Chiang , “Investigation of Local-Strain Effect of Nano-scale Triple Gate SiGe CMOS Transistor”, Published at 3rd Cross-Strait Workshop on Nano Science & Technology, April 27 – 29, 2004, HuaLian, Taiwan.
  209. C.A. Yuan and K.N. Chiang, “Investigation of dsDNA Structure Transition Meso-Mechanics Using Finite Element Method”, Published at 3rd Cross-Strait Workshop on Nano Science & Technology, April 27 – 29, 2004, HuaLian, Taiwan.
  210. C.T. Lin, W.C. Liao, J.Y. Chen, H.C. Su and K.N. Chiang , “Design and Analysis of Nano-Probe of AFM Using Large Deflection Theory “, 3rd Cross-Strait Workshop on Nano Science & Technology, April 27 – 29, 2004, HuaLian, Taiwan.
  211. Peng, C. T. and Chiang, K. N., “Experimental Characterization and Mechanical Behavior Analysis on Intermetallic Compounds of 96.5Sn-3.5Ag and 63Sn-37Pb Solder Bump with Ti-Cu-Ni UBM on Copper Chip”, 54th ECTC International Conference, pp. 90-97, Las Vegas, June 1-4, 2004.
  212. Yuan, C. A. and Chiang, K. N., “Investigation of dsDNA stretching meso-mechanics using finite Element Method”, Published at the 2004 Nanotechnology Conference, March 7-11, 2004, Boston, Massachusetts, U.S.A.
  213. Yuan, C. A., Han, C. N. and Chiang, K. N., “Design and Analysis of Novel WLCSP Structure,” EuroSIME2004 International Conference, May 9-May 12, 2004, Brussels, Belgium.
  214. Chen, J. Y., Lin, C. T., Liao, W. C., Su, H. C., Tsai, C. H. and Chiang, K. N., “A New Nano-Probe Using Micro Assembly Transfer”, Published at First International Nano Bio-Packaging Workshop, March 22-23, 2004, Atlanta.
  215. C. C. Lee, K. N. Chiang, “3D Structure Design and Reliability Analysis of Wafer Level Package with Bubble-Like Stress Buffer Layer”, Published at ITHERM2004 (IEEE/ASME), June 1-4, 2004. Las Vegas.
  216. C. M. Liu and K. N. Chiang, “Solder Interconnection Layout Design and Reliability Enhancement of Wafer Level Packaging”, ICEPT2003, pp. 56-64, Oct. 27-30, ShangHai, China.
  217. C. C. Lee and K. N. Chiang, “Design and Analysis of Temperature Distribution for 2.0L Cylinder Head in Engine Operation,” 2003 CSME annual meeting, Dec. 2003, Taipei.
  218. Peng, C. T., Lee, C. C. and Chiang, K. N., “A Novel Silicon Base Piezoresistive Pressure Sensor Using Front Side Etching Process”, 2003 ASME Intl. Mechanical Engineering Congress and Exposition, Nov. 17-22, 2003, D.C., USA.
  219. Peng, C. T., Lee, C. C. and Chiang, K. N., “Packaging Design of the CMOS Compatible Pressure Sensor Using Flip Chip Technology”, 2003 ASME Intl. Mechanical Engineering Congress and Exposition, Nov. 17-22, 2003, D.C., USA.
  220. Lee, C. C., and Chiang, K. N., "Design and Reliability Analysis of Wafer Level Package with Bubble-Like Buffer Layer", Published at InterPACK2003 International Conference, July, 2003, Hawaii.
  221. Peng, C. T., Liu, C. M. and Chiang, K. N., “The Reliability Analysis and Structure Design for High Density Flip Chip BGA Packaging”, published at EuroSimE2003 (IEEE/ASME), March 30 - April 2, Aix-en-Provence, France.
  222. Yuan, C. A., Liu, H. C., Sun, M. H. and Chiang, K. N., “Design, analysis and validation of vertical probing technology”, published at EuroSIME2003 (IEEE/ASME), March 30 - April 2, Aix-en-Provence, France.
  223. Ku, H. T. and Chiang, K. N., “Design and Reliability Analysis of Two Dimensional Optical Fiber Array Modules”, published at EuroSIME2003 (IEEE/ASME), March 30 - April 2, Aix-en-Provence, France.
  224. Lin, C. T., Peng, C. T., Lin, J. C. and Chiang, K. N., “Analysis and Validation of Sensing Sensitivity of a Piezoresistive Pressure Sensor”, Published at InterPACK2003 (IEEE/ASME), June 30 – July 5, Hawaii, USA.
  225. Kuo, C. T., Yip, M. C. and Chiang, K. N., “Time and Temperature Dependent Mechanical Behavior of Underfill Materials in Electronic Packaging Application”, Published at InterPACK2003 (IEEE/ASME), June 30 – July 5, Hawaii, USA.
  226. Chang, K.C., and Chiang, K.N., "Effect of Cu Stud on Solder Ball Shear Strength", Published at Annual Meeting of Chinese Association of Engineering Mechanics, Dec., 2002.
  227. Chen, K. M. and Chiang, K. N., "Probe Depth Prediction of Integrated Circuit Using Analytical Method", CSME Conference, Nov. 2002.
  228. Liu, C.M., Chiang, K.N., Chen, W.K., and Chen, R.S., "Design and Thermal Stress/Strain Analysis of Cast-In Dry Liner", CSME Conference, Nov. 2002.
  229. Ku, S.T., and Chiang, K.N., "Reliability Analysis of a New Type of Optical Fiber Array Module for Transceivers", CSME Conference, Nov. 2002.
  230. Lin, J. C. and Chiang, K. N., “Design and Analysis of Wafer-Level CSP with Double-Pad-Structure”, Published at ISEM International Conference, Dec. 2002, Taipei.
  231. Liu, C. M. and Chiang, K. N., “Solder Bumps Layout Design and Reliability Enhancement of Wafer Level Packaging”, Published at ISEM International Conference, Dec. 2002, Taipei.
  232. Chang, K. C. and Chiang, K. N., “Aging Effect on Solder Ball Shear Strength”, Published at ISEM International Conference, Dec. 2002, Taipei.
  233. Peng, C. T., Lin, J. G., Lin, J. T and Chiang, K. N., “Design, Analysis and Validation of Silicone-Based High Sensitivity Pressure Sensor”, Published at ISEM International Conference, Dec. 2002, Taipei.
  234. Hsu, S. M., Lin, J. C. and Chiang, K. N., “A Full-Scale 3D Finite Element Analysis for No-Underfill Flip Chip Package”, Published at 2002 ASME Intl. Mechanical Engineering Congress and Exposition, Nov. 17-22, 2002, New Orleans, USA.
  235. Peng, C. T., Lin, J. G., Lin, J. T and Chiang, K. N., "Investigation of Thermal Effect of Packaged CMOS Compatible Pressure Sensor", Published at 2002 ASME Intl. Mechanical Engineering Congress and Exposition, Symposium on Microelectronic Manufacturing, Reliability, and Quality Assurance Testing, Nov. 17-22, 2002, New Orleans, USA.
  236. Peng, C. T. and Chiang, K. N., "Overview of Multilayered Thin Film Theories for MEMS and Electronic Packaging Appications", Published at THERM2002 (IEEE), May 2002, San Diego, USA.
  237. Lin, C. T. and Chiang, K. N., "Reliability Analysis of Flip Chip Packages Using the Contact Finite Element Method", Published (CD-ROM) at Annual Meeting of CSME, Nov. 8, 2001, Taipei.
  238. Liu, C. M., Yuan, C. A. and Chiang, K. N., "Pad Design and Reliability Analysis for Flip Chip Packaging", Published at Annual Meeting of Chinese Association of Engineering Mechanics, Nov., 16, 2001, TaiChung.
  239. Yuan, C. A. and Chiang, K. N.,"Micro to Macro Thermo-Mechanical Simulation of Wafer Level Packaging", published at EuroSimE2001 Conference (IEEE, EI), April 9-11 2001, Paris.
  240. Yeh, M. K., Chiang, K. N. and Su J. A., "Thermal Stress Analysis of Thermally-Enhanced Plastic Ball Grid Array Electronic Packaging", Published at InterPACK2001 International Conference (ASME, EI)), July, 2001, Hawaii.
  241. Lin, C. J. and Chiang, K. N.,"Design and Analysis of Ceramic-TSOP Package", Published at InterPACK2001 International Conference (ASME, EI)), July, 2001, Hawaii.
  242. Cheng H. C., Lee M. H., Chiang K. N. and Chang C. W., "Thermal-Mechanical Analysis of an NCA Type of Chip-On-Glass Assemblies", (ASME, EI) International Mechanical Engineering Congress & Exposition, EEP-Vol.28, Packaging of Electronic and Photonic Devices, pp.43-49, Nov. 2000, Orlando, USA.
  243. Lin Y. T., Peng J. T. and Chiang K. N.,"Parametric Design and Reliability analysis of WIT Wafer Level Packaging", (ASME, EI) EEP-Vol.28, Packaging of Electronic and Photonic Devices, pp.69-78, Nov. 2000, Orlando, USA.
  244. Chiang, K.N. Chang C. W. and J. T. Lin, " Process and Reliability Simulation of Flip Chip using ACF", Proceeding of EPTC 2000 (IEEE, EI), pp. 110-116, Dec. 2000, Singarpore.
  245. Liu C. M. and Chiang K. N., " Solder Shape Design and Thermal Stress/Strain Analysis of Flip Chip Packaging Using Hybrid Method", International Symposium on Electronic Materials and Packaging (IEEE, EI), pp.44-50, Nov.30-Dec.2,2000, HongKong.
  246. Lin J. C. and Chiang K. N., "Thermal/Mechanical Analysis of Novel C-TSOP Using Nonlinear Finite Element Method",. International Symposium on Electronic Materials and Packaging (IEEE, EI), pp.371-377, Nov.30-Dec.2,2000, HongKong.
  247. Liu Z. N., Lin J. D. and Chiang K. N., "A New Approach for No-Underfill Flip Chip Package Design", Published at Proceeding of Mechatronic2000 Conference (IEEE/ASME, EI CD-ROM), Sept. 6-8, 2000. Atalanta, USA.
  248. Chiang K. N. and Liu C. M., "Solder Reflow Prediction of Hybrid Pad Packaging System", The 7th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (IEEE, EI), Vol. II, pp.340-348. May 23-26, 2000. Las Vegas, USA.
  249. Chiang K. N., Liu C. M., "Preditction of Solder Liquid Formation for the Hybrid-Pad-Shapes System of Area Array Packages", (ASME, EI) International Mechanical Engineering Congress & Exposition, 99-IMECE/EEP-28, Nov. 14-19, 1999, Nashville, USA.
  250. Cheng, H. C., Lee, M. H., Chiang, K. N. and Chang, C. W., "Contact Stress Analysis of Chip-on-Glass Assemblies Using the Micro-Bump Bonding Method", (ASME, EI) international Mechanical Engineering Congress & Exposition, MAT-23A, Nov. 14-19, 1999, Nashville, USA.
  251. Chiang, K. N. and Liu, Z. N., "Stacked MultiChip Module Technique of Ball Grid Array Package", (ASME, EI) international Mechanical Engineering Congress & Exposition, MAT-24, Nov. 14-19, 1999, Nashville, USA.
  252. Chiang K. N., Cheng H. C., Liu C. M.,"A Comparison of Thermal Stress/Strain Behavior of Ellipse/Round Solder Pads", 1999 InterPACK, EEP-Vol. 26-1, pp.413-418, Advances in Electronic Packaging (ASME, EI) 1999, Hawaii, USA.
  253. Chiang K. N., Cheng H.C., "On Enhancing Eutectic Solder Joint Reliability Using A 2nd-Reflow-Process Approach", (ASME, EI) Winter Annual Meeting, Thermo-Mechanical Characterization of Evolving Packaging Materials and Structures Symposium, EEP-Vol. 24, pp.21-25, Nov. 15-20, 1998, Anaheim, CA, USA.
  254. Cheng H. C., Chiang K. N., and Chen C. K., "Parametric Analysis of Thermally Enhanced BGA Reliability Using A Finite-Volume-Weighted Averaging Technique", (ASME, EI) Winter Annual Meeting, Thermo-Mechanical Characterization of Evolving Packaging Materials and Structures Symposium, EEP-Vol. 24, pp.13-20, Nov. 15-20, 1998, Anaheim, CA, USA.
  255. Chiang K.N., Lee M.K., and Cheng H.C., "Area Array Solder Joint Design and Reliability Prediction", International Symposium on Advanced IC Packaging Technology, Proc. pp.120-127, April 23, 1998, HsinChu, Taiwan.
  256. Chang Z.M., Chiang K.N., "Parametric Thermal Stress Analysis of Underfill-Encapsulanted Flip Chip Packages", International Symposium on Advanced IC Packaging Technology, Proc. pp.111-119, April 23, 1998, HsinChu, Taiwan.
  257. Chiang K.N., Cheng H.C., and Chen W.H.,"A Hybrid Approach for Ball Grid Array Nonlinear Thermal Stress Analysis", Published at International Conference on Computational Engineering, Oct. 6-9, 1998, Atlanta GA, U.S.A.
  258. Chiang K.N.,"A Large Scale Finite Element Analysis for Ball Grid Array Package Design", Invited paper, HPC'98 Conference, Sept.22-25, 1998, Singapore.
  259. Chiang K.N., Lee M.K., and Cheng H.C., "Area Array Solder Joint Design and Reliability Prediction", International Symposium on Advanced IC Packaging Technology, Proc. pp.120-127, April 23, 1998, HsinChu, Taiwan.
  260. Chang Z.M., Chiang K.N., "Parametric Thermal Stress Analysis of Underfill-Encapsulanted Flip Chip Packages", International Symposium on Advanced IC Packaging Technology, Proc. pp.111-119, April 23, 1998, HsinChu, Taiwan.
  261. Chiang K.N., Cheng H.C., and Chen W.H.,"A Hybrid Approach for Ball Grid Array Nonlinear Thermal Stress Analysis", (EI) International Conference on Computational Engineering, Oct. 6-9, 1998, Atlanta GA, U.S.A.
  262. Chiang K.N.,"A Large Scale Finite Element Analysis for Ball Grid Array Package Design", Invited paper, HPC'98 Conference, Sept.22-25, 1998, Singapore.
  263. Chiang K.N., "Finite Element Analysis for Ball Grid Array", workshop on semiconductor processing, packaging, and material into twenty-first century, April 22-24, 1997, Taiwan.
  264. Chiang K.N., Chen W.L., "Electronic Packaging Reflow Shape Prediction for The Solder Mask Defined Ball Grid Array", The National Conference on the Theoretical and Applied Mechanics, Proceeding Vol. I pp.369-373 Dec. 1997.
  265. Cheng H.C., Chiang K.N., and Lee M.H., "Finite Element Analysis of Plastic Ball Grid Array Packages Using a Local/Global Technique", The National Conference on the Theoretical and Applied Mechanics, Proceeding Vol. II pp.465-474, Dec. 1997.
  266. Chen W.L., Shyu B.L. and Chiang K.N., "Prediction of the Solder Joint Configuration Under Various Geometric parameters", (EI) MED-Vol. 6-1, Manufacturing Science and Technology Volume I, pp.397-400, ASME winter annual meeting, Nov. 16-21 1997, Dallas, Texas, USA.
  267. Cheng H.C., Chiang K.N., and Lee M.H., "On the Equivalent Finite Element Beam Model for Ball Grid Array Analysis", (EI) MED-Vol. 6-1, Manufacturing Science and Technology Volume I, pp.353-360, ASME winter annual meeting, Nov. 16-21 1997, Dallas, Texas, USA.
  268. Chen W.L., Chen C.C. and Chiang K.N., ”Development of a New Spring-Dampers Element for General Structural Analysis”, (EI) 1997 High-Performance Computing Conference, IEEE. pp605-610, April 28 - May 2, 1997, Seoul, Korea.
  269. Cheng H.C., Lee M.H. and Chiang K.N., ”On the Optimal Topological Design of Plate/Shell Like Structures for Frequency Response Optimization Problems”, (EI) 1997 High-Performance Computing Conference, IEEE. pp407-412, April 28 - May 2, 1997, Seoul, Korea.
  270. Chiang K.N., Fu H.H., "Finite Element Vibration Analysis for Zero Inserting Force Socket", (EI) 1996 ASME Winter Annual Meeting, EEP-Vol. 17, pp.81-86,1996 Nov. 17-22, Atlanta, U.S.A.
  271. Fu H. H. and Chiang K. N., “P6 CPU Chip Connector Eigenfrequency Analysis”, The Eighth Annual MSC Taiwan User’s Conference, section I, pp. 6-10, Taipei.
  272. Chiang K.N., Shyu B.L. and H.H. Fu,"The Effect of Indefinite Sparse Solver in LS-NIKE3D", The Second International Conference on Computational Structures Technology, Athens, Greece, Aug.30-Sept.1, 1994.
  273. Chiang K. N., "P-Version Element Assembly Approach in MSC/NASTRAN", The Fifth Annual MSC Taiwan User's Conference, Proc. Vol. I Part 15, Taipei, Nov. 15-16, 1993.
  274. Komzsik L. and Chiang K. N., "A Lagrange Multiplier Based Parallel Algorithm in MSC/NASTRAN", The Fifth Annual MSC Taiwan User's Conference, Proc. Vol. I Part 1, Taipei, Nov. 15-16, 1993.
  275. Chiang K. N. and Fulton R. E., "Advances and Trends in Transient Parallel Finite Element Analysis", 1990 ASME International Computers in Engineering Conference, Proc. Vol. II, pp.433-439, Aug. 5-9, 1990, Boston MA.
  276. Fulton R. E., Chiang K. N. and Goehlich D., "Finite Elements for Concurrent Processing Computers". (EI) 1989 ASME International Computers in Engineering Conference, Conference Proc. Vol. II pp.17-23, July 30 - August 2, 1989, Anaheim, CA.
  277. Chiang K. N. and Fulton R. E., "A General Approach of Parallel/Vector Finite Element Computations", (EI) 6th ASCE Conference in Computing in Civil Engineering Session 36, Sept. 11-13 1989, Atlanta.
  278. Chiang, K. N. and Fulton R. E., "Nonlinear Dynamics Methods for Parallel Computers". (EI) ASCE Fifth Conference on Computing in Civil Engineering, Proc. pp. 144-158, March 29-31, 1988 Alexandria, VA.
  279. Fulton R. E., Chiang K. N. and Goehlich D., "Advanced in Nonlinear Analysis Methods for Ocean Structures using Parallel Computers", Proc. at International Conference on Port and Ocean Engineering Under Arctic Condition June 12-16, 1989, Sweden.
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  281. Fulton, R. E. and Chiang, K. N., "Comparison of Shared Memory and Hypercube Architectures for Structural Dynamics " (Invited Paper), Third International Conference on Supercomputing and Second World Supercomputer Exhibition, Proc. Vol. 1, pp 418-426, May 15-20, 1988, Boston, Massachusetts
  282. Fulton R. E., Chiang K. N. and Goehlich D., "Parallel Computer Implementation of Finite Element Methods", 2nd International Conference on Vector and Parallel Computing June 6-10, 1988, Tromso, Norway.
  283. Connor, L. N. and Chiang, K. N., "Periodically Reversing Heat Transfer and Energy Storage". (EI) ASME winter annual meeting, Dec. 8-12, 1986, Anaheim, CA.

 

 

學生出席國際會議發表論文(2001-2021)

 

2021

S. K. Panigrahy 

A Machine Learning Based Polynomial Regression Model Used for Predict Reliability Life of Wafer Level Package

IMPACT 2021

 Taiwan
 

2021

G. R. Huang(黃冠儒)

Prediction of Fan-Out Level Packaging Warpage Using PSO-based Modified Convolutional Neural Network Model with Laplacian Filter

IMPACT 2021

 Virtual Meeting
 

2020

  

S. K. Panigrahy 

Prediction of Fan-out Panel Level Warpage using Neural Network Model with Edge Detection Enhancement

 		 

ECTC 2020

Florida, USA
 

2019

S. K. Panigrahy 

Reliability Assessment of Wafer Level Packaging using Support Vector Regression Model

IMPACT 2019

  
   

2019

   

M. Y, Chen(陳珉宇)

Prediction of Panel Level Warpage Using Convolution Neural Network Model

 

IMPACT 2019

  
 

2019

  

Y. C. Tseng(曾驛捷)

  

Reliability Prediction of WLP using AI Recurrent Neural Network Regression Model

IMPACT 2019

  
   

2019

  

T. H. Tsai(蔡宗樺)

    

Rebliability Prediction of WLCSP using RF Regression Model

 

EMAP 2019

  
   

2019

  

B. R. Lai(賴柏瑞)

  

AI-Assisted Design-on-Simulation Techology for Advanced Packaging

 		 

EMAP 2019

  

2019

P. H. Chou(周佩勳)

Failure Life Prediction of Wafer Level Packaging using DoS with AI Technology

ECTC 2016

Las Vegas, USA

2019

Y. C. Lee(李育承)

Reliability Assessment of WLCSP using Energy Based Model with Inelastic Strain Energy Density

ICEP2019

Kuwana, Japan

2019

S. W. Liu(劉士瑋)

Warpage and Simulation Analysis of Panel Level FO-WLCSP Using Equivalent CTE

ICEP2019

Kuwana, Japan

2019

Y. H. Liu(劉聿翔)

Trace line Layout Design of FO-WLCSP

ICEP2019

Kuwana, Japan

2018

H. Y. Hsiao(蕭翔云)

Reliability Assessment of Wafer-Level Packaging using Random Forest Regression Model

IMPACT 2018

Taiwan,Taipei

2018

P. H. Chou(周佩勳)

Reliability Assessment of Wafer Level Package using Artificial Neural Network Regression Model

IMPACT 2018

Taiwan,Taipei

2018

Y. T. Shen(沈奕廷)

Reliability Evaluation of I/O Pad Size Effect of FO-WLCSP

IMPACT 2018

Taiwan,Taipei

2018

P. H. Wang(王保雄)

Design And Reliability Assessment of Stacked FAN-OUT Packaging.

SMTA2018

Hawaii, USA

2017

C.Y. Tsou(鄒承諺)

Reliability Assessment using Modified energy based model for WLCSP Solder Joints

ICEP2017

Japan, Yamagata

2017

T.N. Chang(張天寧)

Novel wafer level packaging for large die size device

ICEP2017

Japan, Yamagata

2016

P.L. Wu(吳配倫)

Finite element mesh size effect for reliability assessment of WLCSP using different creep theories

IMPACT 2016

Taiwan,Taipei

2016

Velsankar Ramachandran

Characteristic study of anand and modified anand creep models for area array type WLCSP

IMPACT 2016

Taiwan,Taipei

2016

M.H. Hsu(徐敏軒)

Investigation of thermal cycling maximum temperature effect on fatigue life of WLCSP

ICEP 2016

Takinoyu,Japan

2016

C.J. Chan(詹智如)

Study on current and junction temperature stress aging effect for accelerated aging test of Light emitting diodes

ICEP 2016

Takinoyu,Japan

2016

L. L. Liao (廖莉菱)

Power cycling test and failure mode analysis of high-power module

ICEP 2016

Takinoyu,Japan

2016

K. C. Wu(吳凱強)

Characterization of thermal cycling ramp rate and dwell time effects on AF (Acceleration Factor) Estimation

ECTC 2016

Las Vegas, USA

2016

C. C. Chang(張嘉誠)

A Method to Compensate Packaging Effects on three-axis MEMS Accelerometer

ITherm 2016

Las Vegas, USA

2015

C.H. Lee（李至軒）

Creep effect on life prediction of WLCSP under different ramp rate of thermal cycling

MAM 2015

Greboble, France

2015

L. L. Liao (廖莉菱)

Reliability assessment on the temperature profiles effect of the power module

MAM 2015

Greboble, France

2015

L. L. Liao (廖莉菱)

Study on configuration design of interconnection in high power module

EuroSimE 2015

Budapest, Hungary

2015

H. T. Yang(楊宏徳)

Research on Packing Effects of  Three-axis SOI MEMS Accelerometer

EuroSimE 2015

Budapest, Hungary

2015

F. M. Hsu(徐逢懋)

Determination of the Junction Temperature of Gallium Nitride (GaN)-based High Power LED Under Thermal with Current loading Conditions

ICEP 2015

Kyoto, Japan

2015

C. C. Yang(楊哲嘉)

Analysis of LED Wire Bonding Process Using Arbitrary Lagrangian - Eulerian and Equilibrium Mesh Smoothing Algorithm

ICEP 2015

Kyoto, Japan

2014

F. M. Hsu(徐逢懋)

Thermal Analysis and Reliability Assessment of Power Module under Power Cycling Test Using Global- Local Finite Element Method

ICEP 2014

Toyama, Japan

2014

K. C. Wu(吳凱強)

Investigation of solder creep behavior on wafer level CSP under thermal cycling loading

ICEP 2014

Toyama, Japan

2014

K. C. Wu(吳凱強)

Investigation of Strain Rate Effect on Lifetime Performance of Wafer Level CSP Under Different Thermal Cycling Loading Rate

iMPACT 2014

Taipei, Taiwan

2014

L. L. Liao (廖莉菱)

Study on configuration design of interconnection in high power module

EuroSimE 2014

Gent, Belgien

2014

Y. F. Su (蘇彥輔)

Study on Thermal Induced Stress Hysteresis Behavior of Thin Film Sensor

ThinFilms 2014

Chongqing, China

2014

Y. F. Su (蘇彥輔)

Development of a Feasible Simulation Methodology for Residual Stress Assessment of Multilayer Thin Film Structure

ThinFilms 2014

Chongqing, China

2014

Y. F. Su (蘇彥輔)

Acceleration Factor Analysis of Aging Test on Gallium Nitride (GaN)-based High Power Light-emitting Diode (LED)

ITherm 2014

Orlando, USA

2014

Y. F. Su (蘇彥輔)

Structure design and reliability assessment of double-sided with double-chip stacking packaging

EuroSimE 2014

Gent, Belgien

2013

Y. C. Chiang(江佾澈)

Investigating the Temperature Effect of Reliability on Integration IC 3D Packaging under Drop Test

EPTC2013

Singapore

2013

Y. F. Su(蘇彥甫)

Analysis of LED Wire Bonding Process Using Arbitrary Lagrangian-Eulerian and Explicit Time Integration Methods

iMPACT2013

Taipei, Taiwan

2013

C. J. Huang (黃昭荏)

The Mechanical Properties of Carbon Nanotubes Ropes Using Atomistic-Continuum Mechanics and the Equivalent Methods

ICCES 2013

Seattle, USA

2013

Y. F. Su(蘇彥甫)

Development of Double-Sided with Double-Chip Stacking Structure using Panel Level Embedded Wafer Level Packaging

ECTC 2013

Las Vegas, USA

2013

T. Y. Hung(洪端佑)

Bonding Wire Life Prediction Model of the Power Module under Power Cycling Test

EuroSimE 2013

Poland

2013

L. L. Liao (廖莉菱)

Electro-thermal finite element analysis and verification of power module with aluminum wire

MAM 2013

Leuven, Belgium

2013

L. L. Liao (廖莉菱)

Thermo-electric finite element analysis and characteristic of thermoelectric generator with intermetallic compound

MAM 2013

Leuven, Belgium

2013

C. F. Huang (黃建富)

Research on the degradation of AlGaInP Ultra High Brightness LEDs influenced by ohmic metal design

MAM 2013

Leuven, Belgium

2013

H. C. Huang(黃湘珺)

The Solder Creep Behavior of Power Module Subject to Temeperature Cycling Test with Different Temperature Profiles

ICEP 2013

Osaka, Japan

2012

Y. H. Yang(楊喻翔)

A Thermal Performance Assessment of Panel Type Packaging (PTP) Technology for High Efficiency LED

ICEMP 2012

Hong Kong

2012

Y. F. Su (蘇彥輔)

Reliability Analysis of 3D IC Integration packaging under Drop Test Condition

iMPACT 2012

Taipei, Taiwan

2012

Y. F. Su (蘇彥輔)

Investigation of Interconnect Design on Interfacial Cracking Energy of Al/TiN Barriers under a Flexural Load

ThinFilms 2012

Singapore

2012

C. F. Huang (黃建富)

Quantum Efficiency Investigation at high Current Density of Ultra-High-Brightness LEDs

ITHERM 2012

San Diego, USA

2012

C. T. Lai (賴致廷)

Investigation on the Effect of Surface Roughness on the Fracture Strength of SCS

EuroSimE 2012

Lisbon, Portugal

2012

L. L. Liao (廖莉菱)

Development and analysis of the thermoelectric material with intermetallic compound

ICEP 2012

Tokyo, Japan

2012

L. L. Liao (廖莉菱)

External Stress Effect to Electromigration on Thermal Annealed and Residual Stress Controlled Aluminum Strip

ICEP 2012

Tokyo, Japan

2012

T. Y. Hung (洪端佑)

Residual Stress Effect of Electromigration Behavior on Aluminum Strip

MAM 2012

Grenoble, France

2012

T. Y. Hung (洪端佑)

Thermal Cycling Period Effect of Fatigue Life of the Power Module

MAM 2012

Grenoble, France

2012

C. J. Huang (黃昭荏)

Analysis of the Mechanical Properties of Si/SiGe Heterostructure using Atomistic-continuum Mechanics with Constraint Equations

APMC-10, ICONN 2012 & ACMM-22

Perth, WA Australia

2011

Y. F. Su (蘇彥輔)

Determination of Silicon Die Initial Crack Using Acoustic Emission Technique

iMPACT 2011

Taipei, Taiwan

2011

T. Y. Hung (洪端佑)

Dwell Time Effect and Thermal Fatigue Life Assessment of Power Module

EMAP2011

Kyoto, Japan

2011

T. Y. Hung (洪端佑)

Thermal-mechanical behavior of the bonding wire for a power module subjected to the power cycling test

ESREF2011

Bordeaux, France

2011

S. Y. Yang (楊炘岳)

Measurement and  simulation  of  interfacial  adhesion strength between SiO2 thin film and III-V material

ESREF2011

Bordeaux, France

2011

H.J. Wang (王涵融)

Thin Film Residual Stress Assessment of Capacitive MEMS Microphones Using Process ModelingTechnology

InterPACK2011

Portland, USA

2011

P.C. Chen (陳珮綺)

Determination and Verification of Silicon Die Strength Using Ball-Breaker Test

InterPACK2011

Portland, USA

2011

S.Y. Chiang (江室瑩)

Electro-Thermal Analysis of the Insulated Gate Bipolar Transistor Module Subjected to Power Cycling Test Using Specified Boundary Condition Technology

EuroSimE2011

Linz, Austria

2011

Y. F. Su (蘇彥輔)

Stress/Stain Assessment and Reliability Prediction of Through Silicon Via and Trace Line Structures of 3D Packaging

EuroSimE2011

Linz, Austria

2010

C. J. Huang (黃昭荏)

Research on Multi-Scale Structural Analysis using the Atomistic-Continuum Equivalent Mechanics

CSWNST-8

Hong Kong

2010

T. Y. Hung (洪端佑)

Reliability Assessment of 3D Chip Stacking Package Using Metal Bonding and Through Silicon Via Technologies

ASME-IMECE

Vancouver, Canada

2010

C. J. Huang (黃昭荏)

Carbon Nanotubes Structural Mechanics Using the Atomistic-Continuum Mechanics and Equivalent Methods

ACCM-7

Taipei, Taiwan

2010

S.Y. Chiang (江室瑩)

Life Prediction of High Concentration Photovoltaic Modules Subjected to Thermal Cycling Test

IMPACT2010

Taipei, Taiwan

2010

S. Y. Yang(楊炘岳)

Strength Determination of Light-emitting diodes and Chip Structure Design

IMPACT2010

Taipei, Taiwan

2010

S. Y. Yang(楊炘岳)

Determination of Maximum Strength and Optimization of LED Chip Structure

ESTC2010

Berlin, Germany

2010

Y. F. Su (蘇彥輔)

A Study on the Thermal Performance of a Chip-in-substrate-type LED Package Structure

ICSJ2010

Tokyo, Japan

2010

T. Y. Hung (洪端佑)

Thermal Design and Transient Analysis of Insulated Gate Bipolar Transistors of Power Module

Itherm2010

 Las Vegas, USA

2010

T. L. Chou (周宗燐)

Transient Thermal Analysis of High-Concentration Photovoltaic Cell Module Subjected to Coupled Thermal and Power Cycling Test Conditions

Itherm2010

 Las Vegas, USA

2010

C. J. Wu (吳仲融)

Delamination Investigation of Copper Bumps in 3D Chip Stacking Packages Using the Modified Virtual Crack Closure Technique

ICEP2010

Sapporo, Japan

2010

S.Y. Chiang (江室瑩)

Temperature Dependent Current Crowding Analysis of Insulated Gate Bipolar Transistor

ICEP2010

Sapporo, Japan

2010

Y. F. Su (蘇彥輔)

Light Degradation Prediction of High Power Light Emitting Diode Lighting Modules

EuroSimE2010

Bordeaux, France

2010

C. J. Wu (吳仲融)

InterfaciProcess Integration for 3D Chip Stacking with Thin Wafer Handling Technology

MAM2010

Belgium

2010

H. H. Chang (張香鈜)

Process Integration for 3D Chip Stacking with Thin Wafer Handling Technology

MAM2010

Belgium

2010

S.Y. Chiang (江室瑩)

Life Prediction of HCPV Under Thermal Cycling Test Condition

MAM2010

Belgium

2010

T. L. Chou (周宗燐)

Overview and Applicability of Residual Stress Estimation of Film-Substrate Structure

ICAM2010

Kenting, Taiwan

2010

H. A. Teng(鄧宏安)

A Robust Nano-Mechanics Approach for Tensile and Modal Analysis Using Atomistic-Continuum Mechanics Method

ICONN 2010

Sydney, Australia

2009

S. Y. Yang(楊炘岳)

Warpage Analysis of High Power InGaN Light Emitting Diodes after Laser Lift-off

EMAP 2009

Penang, Malaysia

2009

S.Y. Chiang (江室瑩)

Non-Uniform Thickness Effect of Die Bonding Interface in
High-Concentration Photovoltaic Module

EMAP 2009

Penang, Malaysia

2009

S. Y. Yang(楊炘岳)

Reliability Analysis of Copper Interconnections of System-in-Packaging 

IMPACT2009

Taipei, Taiwan

2009

C.J. Huang(黃昭荏)

Reliability and Parametric Study on Chip Scale Package Under Board-Level Drop Test

IMPACT2009

Taipei, Taiwan

2009

T. L. Chou (周宗燐)

Fabrication Process Simulation and Reliability Improvement of High- brightness LEDs

ESREF2009

Arcachon, France

2009

C. Y. Chou (周展延)

Metal trace impact life prediction model for stress buffer enhanced package

EMPC2009

Rimini, Italy

2009

T. Y. Hung (洪端佑)

A study of thermal performance for chip-in-substrate package on package

EMPC2009

Rimini, Italy

2009

H. H. Chang(張香鋐)

3D Stacked Chip Technology Using Bottom-up Electroplated TSVs

ECTC 2009

San Diego, USA

2009

C.J. Huang(黃昭荏)

Dynamic Study and Structure Enhancement of Small Outline Dual-in-line Memory Module

EuroSimE2009

Delft, Netherlands

2009

M. Sano(佐野雅文)

Uncertainty and Reliability Analysis of Chip Scale Package Subjected to Board-level Drop Test

EuroSimE2009

Delft, Netherlands

2009

C. J. Wu (吳仲融)

Die-Cracking Evaluation of Silicon Chip Covered with Polymer Film for 3D Chip Stacking Packages

ICEP 2009

Kyoto, Japan

2009

W. H. Chi (紀偉豪)

Analysis of Thermal Performance for High Power Light Emitting Diodes Lighting Module

ICEP 2009

Kyoto, Japan

2009

C. J. Wu (吳仲融)

Strength Evaluation of Silicon Die for 3D Chip Stacking Packages Using ABF as Dielectric and Barrier Layer in Through-Silicon Via

MAM2009

Grenoble, France

2009

Chiu, C. C.(邱建嘉)

Investigation of the Delamination Mechanism of the Thin Film Dielectric Structure in Flip Chip Packages

MAM2009

Grenoble, France

2008

W. H. Chi (紀偉豪)

Analysis of Thermal Performance of High Power Light Emitting Diodes Package

EPTC2008

Singapore

2008

T. Y. Hung (洪端佑)

Validation and reliability assessment of board level drop test of chip-scale-packaging

ICEM2008

Nanjing, China

2008

M. C. Yew (游明志)

Reliability Analysis of the Panel Base Package (PBPTM) Technology with Enhanced Cover Layer

IMPACT2008

Taipei, Taiwan

2008

C. Y. Chou (周展延)

Investigation of influences of PCB on board-level drop test by dynamic simulation and modal analysis

IMPACT2008

Taipei, Taiwan

2008

C. Y. Chou (周展延)

Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact

ESREF 2008

Maastricht, Netherland

2008

C. J. Wu (吳仲融)

Reliability and Thermal Assessment of Stacked Chip-on-Metal Panel Based Package (PBPTM) with Fan-Out Capability

ESTC 2008

London, England

2008

T. L. Chou (周宗燐)

Investigation of Thermal Performance of High-Concentration Photovoltaic Solar Cell System

23rd EU PVSEC

Valencia, Spain

2008

H. H. Chang(張香鋐)

TSV Process Using Bottom-up Cu Electroplating and its Reliability Test

ESTC2008

Greenwich, UK

2008

S. Y. Yang(楊炘岳)

Reliability Analysis of Copper Interconnections of System-in-Packaging Structure using Finite Element Method

ICEPT 2008

Shanghai, China

2008

M. C. Yew (游明志)

A Study of Thermal Performance for the Panel Base Package (PBPTM) Technology

ICEPT 2008

Shanghai, China

2008

M. C. Yew (游明志)

Trace Line Failure Analysis and Characterization of the Panel Base Package (PBPTM) Technology with Fan-Out Capability

ITherm 2008

Florida, USA

2008

C. N. Han (韓政男)

Sappire-removed induced the deformation of high power InGaN light emitting diodes

EuroSimE2008

Freiburg im Breisgau, Germany

2008

C. Y. Chou (周展延)

Investigation of Stress-buffer-enhanced Package Subjected to Board-level Drop Test

EuroSimE2008

Freiburg im Breisgau, Germany

2008

C. J. Wu (吳仲融)

Estimation and Validation of Elastic Modulus of Carbon Nanotubes Using Nano-Scale Tensile and Vibrational Analysis

ICCES'08

Hawaii, USA

2008

T. L. Chou (周宗燐)

Cracking energy estimation of ultra low-k package using novel prediction approach combined with global-local modeling technique

MAM2008

Dresden, Germany

2008

T. L. Chou (周宗燐)

Analysis of Cu/Low-k Structure under Back End of Line Process

MAM2008

Dresden, Germany

2007

T. L. Chou (周宗燐)

Investigation of Thermal Performance of High-Concentration Photovoltaic Solar Cell Package

EMAP2007

Daejeon, Korea

2007

S.Y. Chiang (江室瑩)

Reliability Analysis of Copper Interconnection in System-in-package Structure

EMAP2007

Daejeon, Korea

2007

C.J. Huang (黃昭荏)

Investigation of the mechanical properties of nano-scale metallic crystal structural with point defects

ENS'07

Paris, France

2007

M. C. Yew (游明志)

A Study of Material Effects for the Panel Level Package (PLP) Technology

IMPACT2007

Taipei, Taiwan

2007

T. L. Chou (周宗燐)

Investigation of the Hysteresis Phenomenon of A Silicon-based Piezoresistive Pressure Sensor

IMPACT2007

Taipei, Taiwan

2007

M. C. Yew (游明志)

A Study of Failure Mechanism and Reliability Assessment for the Panel Level Package (PLP) Technology

EuroSIME2007

London, England

2007

C. Y. Chou (周展延)

Estimation and validation of mechanical properties of single crystal silicon by atomic-level numerical model

ICEM13

Alexandroupolis, Greece

2007

C. J. Wu (吳仲融)

Simulation and Validation of CNT Mechanical Properties – The Future Interconnection Material

ECTC 2007

Reno, USA

2007

M. C. Yew (游明志)

Reliability Assessment for Solders with a Stress Buffer Layer using Ball Shear Strength Test and Board-level Finite Element Analysis

ESREF 2007

Arcachon, France

2007

C. C. Chiu (邱建嘉)

Reliability of Interfacial Adhesion in a Multi-Level Copper/Low-k Interconnect Structure

ESREF 2007

Arcachon, France

2007

C. N. Han (韓政男)

Investigation of dsDNA Molecule Mechanical Behavior Using Atomistic Continuum Mechanics Method

NSTI Nanotech2007

Santa Clara, USA

2007

C. N. Han (韓政男)

Investigation of Mechanical Strength of The Nanoshell of Bacteriophage Phi-29

NSTI Nanotech2007

Santa Clara, USA

2007

C. Y. Chou (周展延)

Thermal Management on Hot Spot Elimination / Junction Temperature Reduction for High Power Density RF Multi-chip Module

Thermal Stress 2007

Taipei, Taiwan

2007

C. C. Chiu (邱建嘉)

Thermal management on hot spot elimination / junction temperature reduction for high power density system in package structure

InterPACK 2007

Vancouver, BC, Canada

2007

H. P. Wei (魏修平)

Failure mode and thermal performance analysis of stacked panel level package (PLP)

InterPACK 2007

Vancouver, BC, Canada

2007

C. C. Chiu (邱建嘉)

Study of Lamina Fracture of Cu/Low-k Interconnects Using the J-Integral Method

FEOFS 2007

Urumqi, CHINA

2006

C.J. Huang (黃昭荏)

Validation of mechanical properties of the nanoscale single crystal IV-A group material by Atomistic-Continuum Mechanics Model

The 30th Conference of Theoretical and Applied Mechanics

Taiwan

2006

M. C. Yew (游明志)

Factorial Analysis of Chip-on-Metal WLCSP Technology with Fan-Out Capability

IPFA2006

Singapore

2006

C. C. Chiu (邱建嘉)

Interconnect Design and Thermal Stress/Strain Analysis of Flip Chip Packaging

ICEM 2006

Jeju, Korea

2006

M. C. Yew (游明志)

Reliability and Characterization of Novel WLCSP with Fan-Out Capability

IMAPS-Taiwan 2006

Taiwan

2006

M. C. Yew (游明志)

Using FEM-based Method for Sensitivity Design of Chip-in-Substrate-Package

IMAPS-Taiwan 2006

Taiwan

2006

C. C. Chiu (邱建嘉)

A Novel Prediction Technique for Interfacial Crack Growth of Electronic Interconnect

ICEM 2006

Jeju, Korea

2006

T. L. Chou (周宗燐)

Investigation of packaging effect of silicon-based piezoresistive pressure sensor

ASME Intl. Mechanical Engineering Congress and Exposition

Chicago, USA

2006

C. J. Wu (吳仲融)

Investigation of Carbon Nanotube Mechanical Properties Using The Atomistic-Continuum Mechanics Method.

NSTI Nanotech 2006

Boston, Massachusetts, USA

2006

C. N. Han (韓政男)

Investigation of ssDNA Backbone Molecule Mechanical Behavior Using Atomistic-Continuum Mechanics Method

NSTI Nanotech 2006

Boston, Massachusetts, U.S.A.

2006

M. C. Yew (游明志)

Reliability Analysis of a New Soft Joint Protection Technology Using in WLCSP

IMPACT 2006

Taiwan

2006

C. N. Han (韓政男)

From Atomic-Level Lattice Structure to Estimate the Silicon Mechanical Bulk Behavior Using the Atomistic-Continuum Mechanics

ACCM-5

Hong Kong

2006

M. C. Yew (游明志)

Sensitivity Design of Chip-in-Substrate-Package Using DOE with Factorial Analysis Technology

EuroSIME2006

Como (Milano), Italy

2006

C. Y. Chou (周展延)

Reliability Impact of Highly Temperature-Dependent Underfill Material to the Lead-Free Flip Chip Package

EuroSimE2006

Como (Milano), Italy

2006

C. C. Lee (李建成)

Electromigration Study of SnAg3.0Cu0.5 Flip Chip Solder Bumps

The 2006 Pan Pacific Microelectronics Symposium

Hawaii, USA

2006

C. T. Lin (林俊德)

Investigation of Nano-Scale Single Crystal Silicon Using the Atomistic-Continuum Mechanics with Stillinger-Weber Potential Function

NanoSingapore 2006

Singapore

2006

H. P. Wei (魏修平)

Reliability Analysis of a Package-on-Package Structure Using Novel WLCSP Technology with Fan-Out Capability

8th International Conference on Electronics Materials and Packaging

Hong Kong

2006

M. C. Yew (游明志)

The Solder on Rubber (SOR) Interconnection Design and Its Reliability Assessment Based on Shear Strength Test and Finite Element Analysis

ESREF 2006

Wuppertal, Germany

2006

C. C. Chiu (邱建嘉)

Electromigration Characteristic of SnAg3.0Cu0.5 Flip-Chip Interconnection

ECTC 2006

San Diego, CA, USA

2006

C. C. Chiu (邱建嘉)

STABILITY OF J-INTEGRAL CALCULATION IN THE CRACK GROWTH OF COPPER/LOW-K STACKED STRUCTURES

ITherm 2006

San Diego, CA, USA

2006

C. J. Wu (吳仲融)

Numerical Simulation of the Mechanical Properties of Carbon Nanotube Using the Atomistic-Continuum Mechanics

European Nano System 2006

Paris, France

2005

C. J. Wu (吳仲融)

Numerical Simulation of the Mechanical Properties of Nanoscale Metal Clusters Using the Atomistic-Continuum Mechanics Method

European Nano System 2005

Paris, France

2005

C. N. Han (韓政男)

Investigation of ssDNA molecule using clustered atomistic method and its application to the dsDNA analysis

Microelectronics, MEMS, and Nanotechnology

Brisbane, Australia

2005

M. C. Yew (游明志)

Reliability Analysis of a New Soft Joint Protection Technology Using in WLCSP

Taiwan ANSYS Users Conference

Taiwan

2005

C. N. Han (韓政男)

Local-Strain Effect of the SiNx/Si Stacking and Nano-Scale Triple Gate Si/SiGe MOS Transistor

Microelectronics, MEMS, and Nanotechnology

Brisbane, Australia

2005

C. T. Lin (林俊德)

Thermal and Mechanical Responses of Thermomechanical Microprobe for High Density Storage Technology

Microelectronics, MEMS, and Nanotechnology

Brisbane, Australia

2005

C. A. Yuan (袁長安)

Investigation of Sequence-Dependent dsDNA Mechanical Behavior using Clustered Atomistic-Continuum Method

Nanotech Conference

Anaheim, USA

2005

C. N. Han (韓政男)

Investigation of Local-Strain Effect of the Nano-Scale Triple Gate Si/SiGe and SiNx/Si Stacking MOS Transistor

Nanotech Conference

Anaheim, USA

2005

C. C. Lee (李昌駿)

Reliability Analysis of WLCSP Using Tie-Release Crack Prediction Finite Element Technique

ASME International Mechanical Engineering Congress & Exposition

Orlando, Florida, USA

2005

C. Y. Chou (周展延)

Solder Joints Layout Design and Reliability Enhancement of Wafer Level Packaging

EuroSimE2005

Berlin, Germany

2005

C. T. Peng (彭治棠)

Thermal Performance and Solder Joint Reliability for Board Level Assembly of Modified Leadframe Module

EuroSimE2005

Berlin, Germany

2005

C. C. Chiu (邱建嘉)

Reliability Assessment of Lead-Free Flip Chip Package Using Factorial Design Methodology

IPACK2005

San Francisco, California, USA

2005

M. C. Yew (游明志)

A NOVEL WLCSP USING SOFT JOINT PROTECTION TECHNOLOGY

IPACK2005

San Francisco, California, USA

2004

C. C. Lee (李昌駿)

Design of Double Layer WLCSP Using DOE with Factorial Analysis Technology

EPTC 2004

Singapore

2004

C. C. Lee (李昌駿)

A Novel WLCSP Technology with High Reliability, Low Cost and Ease of Fabrication

EPTC 2004

Singapore

2004

C. A. Yuan (袁長安)

Atomistic to Continuum Mechanical Investigation of ssDNA and dsDNA using Transient Finite Element Method

Inter-Pacific Workshop on Nanoscience and Nanotechnology

Hong Kong

2004

C. T. Lin (林俊德)

Design and Analysis of a Nano-Probe for the AFM based on the Small/Large Deflection Theory

ASME Intl. Mechanical Engineering Congress and Exposition

Anaheim, USA

2004

C. C. Lee (李建成)

RF Substrate Via Relative Issue Discussion - Via and Ni/Au Surface Layer Crack

7th VLSI Packaging Workshop of Japan

Kyoto, Japan

2004

C. A. Yuan (袁長安)

Investigation of dsDNA stretching meso-mechanics using finite Element Method

2004 Nanotechnology Conference

Boston, Massachusetts, U.S.A.

2004

C. A. Yuan (袁長安)

Design and Analysis of Novel WLCSP Structure

EuroSIME2004

Brussels, Belgium

2004

C. C. Lee (李昌駿)

Analysis of Reliability and Coupling of Efficiency for BGA Type Transceiver

ITHERM2004

Las Vegas, USA

2004

C. C. Lee (李昌駿)

3D Structure Design and Reliability Analysis of Wafer Level Package with Bubble-Like Stress Buffer Layer

ITHERM2004

Las Vegas, USA

2004

C. T. Peng (彭治棠)

Experimental Characterization and Mechanical Behavior Analysis on Intermetallic Compounds of 96.5Sn-3.5Ag and 63Sn-37Pb Solder Bump with Ti-Cu-Ni UBM on Copper Chip

ECTC 2004

Las Vegas, USA

2003

C. T. Peng (彭治棠)

A Novel Silicon Base Piezoresistive Pressure Sensor Using Front Side Etching Process

2003 ASME Intl. Mechanical Engineering Congress and Exposition

D.C., USA

2003

C. A. Yuan (袁長安)

Packaging Design of the CMOS Compatible Pressure Sensor Using Flip Chip Technology

2003 ASME Intl. Mechanical Engineering Congress and Exposition

D.C., USA

2003

C. T. Peng (彭治棠)

The Reliability Analysis and Structure Design for High Density Flip Chip BGA Packaging

EuroSimE2003

France

2003

C. A. Yuan (袁長安)

Design, analysis and validation of vertical probing technology

EuroSimE2003

France

2003

C. A. Yuan (袁長安)

Design and Reliability Analysis of Two Dimensional Optical Fiber Array Modules

EuroSimE2003

France

2003

C. T. Lin (林俊德)

Analysis and Validation of Sensing Sensitivity of a Piezoresistive Pressure Sensor

InterPACK2003 International Conference

Hawaii, USA

2003

C. C. Lee (李昌駿)

Design and Reliability Analysis of Wafer Level Package with Bubble-Like Buffer Layer

InterPACK2003 International Conference

Hawaii, USA

2002

J. C. Lin (林基正)

A Full-Scale 3D Finite Element Analysis for No-Underfill Flip Chip Package

ASME Intl. Mechanical Engineering Congress and Exposition

New Orleans, USA

2002

C. T. Peng (彭治棠)

Investigation of Thermal Effect of Packaged CMOS Compatible Pressure Sensor

ASME Intl. Mechanical Engineering Congress and Exposition, Symposium on Microelectronic Manufacturing, Reliability, and Quality Assurance Testing

New Orleans, USA

2002

C. M. Liu (劉昌明)

Overview of Multilayered Thin Film Theories for MEMS and Electronic Packaging Appications

THERM2002, USA

San Diego, USA

2001

C. A. Yuan (袁長安)

Micro to Macro Thermo-Mechanical Simulation of Wafer Level Packaging

EuroSimE2001, USA

Paris

2001

C. M. Liu (劉昌明)

Thermal Stress Analysis of Thermally-Enhanced Plastic Ball Grid Array Electronic Packaging

InterPACK2001, USA

Hawaii, USA

2001

J. C. Lin (林基正)

Design and Analysis of Ceramic-TSOP Package

InterPACK2001, USA

Hawaii, USA