latest update : 2009.03.09

 　

游明志  Jason, Ming-Chih Yew

　

E-mail : MingChih.Yew@gmail.com

　

Advanced Packaging Research Center

Adv. Microsystem Packaging and Nano-Mechanics Res. Lab.

　

Power Mechanical Engineering, National Tsing Hua University

Room 407, Dept. Power Mechanical Engineering

　

101, Section 2 Kuang Fu Road, Hsinchu, Taiwan 300, Republic of China

　

Curriculum Vitae:

        Education :      2004.06 ~ 2009.01         (Ph.D.)               Department of Power Mechanical Engineering,

                                                                                                 National Tsing Hua University, Taiwan, R.O.C.

                                1999.09 ~ 2003.06         (B.A.)                Study at Department of Power Mechanical Engineering,

                                                                                                 National Tsing Hua University, Taiwan, R.O.C.

                                1997.09 ~ 1999.06                                   National HsinChu High School, Taiwan, R.O.C.

　

Issued Patents:

  1. Ming-Chih Yew, Chien-Chia Chiu, Kuo-Ning Chiang, and Wen-Kun Yang, US patent published no. 20080142941. "3D ELECTRONIC PACKAGING STRUCTURE WITH ENHANCED GROUNDING PERFORMANCE AND EMBEDDED ANTENNA," published on June 19, 2008

  2. Ming-Chih Yew, Chang-Ann Yuan, Chan-Yen Chou, and Kuo-Ning Chiang, US patent published no. 20070296065, "3D electronic packaging structure having a conductive support substrate", published on December 27, 2007

  3. Ming-Chih Yew, Chang-Ann Yuan, Chan-Yen Chou, and Kuo-Ning Chiang, Taiwan patent no. I269460, "A 3D electronic packaging structure using conductive substrate", 2006.12.21

  4. Ming-Chih Yew, Chien-Chia Chiu, and Kuo-Ning Chiang, Taiwan patent no. I264103, "A 3D electronic packaging structure with enhanced grounding performance and embedded antenna", 2006.10.11

  5. Chang-Chun Lee, Kuo-Ning Chiang, Cheng-Nan Han, and Ming-Chih Yew, Taiwan patent no. I233192, "The wafer level structure of system packaging with stacked packaging units", 2005.05.21

　

Main Projects:

  1. 清華大學/育霈科技計畫合作案, 新型可堆疊式系統級封裝技術之產品可靠度與散熱特性分析 (The Reliability Assessment and Thermal Performance Evaluation for Novel Stackable System-in-Package Technology),   2008.03 ~ 2009.02

  2. 工業技術研究院 電子與光電工業研究所 專利搜尋, 三維堆疊式晶片發展技術,   2008.02 ~ 2008.12

  3. 清華大學/育霈科技計畫合作案, 新型可滑動之彎曲導線式晶圓級晶片尺寸構裝之可靠度分析-Ⅲ (The Reliability Analysis of Novel Slide-able Cu Trace Wafer Level Chip Scale Package Ⅲ),   2007.03 ~ 2008.02

  4. 清華大學/育霈科技計畫合作案, 新型可滑動之彎曲導線式晶圓級晶片尺寸構裝之可靠度分析-Ⅱ (The Reliability Analysis of Novel Slide-able Cu Trace Wafer Level Chip Scale Package Ⅱ),   2006.03 ~ 2007.02

  5. 清華大學/育霈科技計畫合作案, 新型可滑動之彎曲導線式晶圓級晶片尺寸構裝之可靠度分析-Ⅰ The Reliability Analysis of Novel Slide-able Cu Trace Wafer Level Chip Scale PackageⅠ),   2005.06 ~ 2006.02

  6. 台積電/清華大學從事半導體合作研究計畫, Interfacial stress, adhesion, crack propagation simulation of multilayer and stacked structure of low-k chip,   2005.02 ~ 2006.01

  7. 工業技術研究院 電子工業研究所 自主性前瞻計畫, 5X/16X Product Design and Development Procedure,   2004.01 ~ 2004.12

  8. 工業技術研究院 電子工業研究所 專利搜尋, Stretchable Circuit 相關結構、設計,   2005.08 ~ 2008.02

　

Journal papers:

  1. Ming-Chih Yew, Mars Tsai, Dyi-Chung Hu, Wen-Kun Yang, and Kuo-Ning Chiang, "Reliability Analysis of a Novel Fan-Out Type WLP," accepted and will be published in Soldering & Surface Mount Technology, April 2009.

  2. M. C. Yew, C. Yuan, C. J. Wu, D. C. Hu, W. K. Yang, and K. N. Chiang, "Investigation of the Trace Line Failure Mechanism and Design of Flexible Wafer Level Packaging," accepted and will be published in IEEE Transactions on Advanced Packaging, 2009.

  3. Chan-Yen Chou, Tuan-Yu Hung, Shin-Yueh Yang, Ming-Chih Yew, Wen-Kun Yang, and Kuo-Ning Chiang, "Solder Joint and Trace Line Failure Simulation and Experimental Validation of Fan-Out Type Wafer Level Packaging Subjected to Drop Impact," Microelectronics Reliability, Vol. 48, pp. 1149-1154, 2008.

  4. Ming-Chih Yew, Chan-Yen Chou, and Kuo-Ning Chiang, "Reliability Assessment for Solders with a Stress Buffer Layer using Ball Shear Strength Test and Board-level Finite Element Analysis," Microelectronics Reliability, Vol. 47, No. 9-11, pp. 1658-1662, 2007.

  5. M. C. Yew, C. Y. Chou, C. S. Huang, W. K. Yang, and K. N. Chiang, "The Solder on Rubber (SOR) Interconnection Design and Its Reliability Assessment Based on Shear Strength Test and Finite Element Analysis," Microelectronics Reliability, Vol. 46, No. 9-11, pp. 1874-1879, 2006.

  6. Ming-Chih Yew, Chien-Chia Chiu, Shu-Ming Chang, and Kuo-Ning Chiang, "A Novel Crack and Delamination Protection Mechanism for a WLCSP Using Soft Joint Technology," Soldering & Surface Mount Technology, Vol. 18, Issue 3, pp. 3-13, 2006.

  7. C. A. Yuan, C. N. Han, M. C. Yew, C. Y. Chou, and K. N. Chiang, "Design, Analysis and Development of Novel Three-Dimensional Stacking WLCSP," IEEE Transactions on Advanced Packaging, Vol. 28, No. 3, pp. 387-396, August 2005.

Conference papers:

  1. Ming-Chih Yew, Chun-Fai Yu, Mars Tsai, Dyi-Chung Hu, Wen-Kung Yang, and Kuo-Ning Chiang, "Reliability Analysis of the Panel Base Package (PBPTM) Technology with Enhanced Cover Layer," Proceedings of the 3rd International Microsystems, Packaging, Assembly and Circuits Technology (IMPACT) Conference and the 10th International Conference on Electronics Materials and Packaging (EMAP), pp. 384-387, October 22-24, 2008, Taipei, Taiwan. (Best Student Paper Award)

  2. Chan-Yen Chou, Tuan-Yu Hung, Shin-Yueh Yang, Ming-Chih Yew, and Kuo-Ning Chiang, "Solder Joint and Trace Line Failure Simulation and Experimental Validation of Fan-Out Type Wafer Level Packaging Subjected to Drop Impact," Proceedings of the 19th European Symposium Reliability of Electron Devices, Failure Physics and Analysis, ESREF2008, pp. 1149-1154, September 29 - October 2, 2008, Maastricht, Netherlands.

  3. Hsiu-Ping Wei, Ming-Chih Yew, Chung-Jung Wu, and Kuo-Ning Chiang, "Reliability and Thermal Assessment of Stacked Chip-on-Metal Panel Based Package (PBPTM) with Fan-Out Capability, "Proceedings of the 2nd Electronics Systems-Integration Technology Conference, pp. 327-332, September 1-4, 2008, Greenwich, UK.

  4. Ming-Chih Yew, Chun-Fai Yu, Mars Tsai, Dyi-Chung Hu, Wen-Kung Yang, and Kuo-Ning Chiang, "A Study of Thermal Performance for the Panel Base Package (PBPTM) Technology, " Proceedings of International Conference on Electronic Packaging Technology and International Symposium on High Density Packaging, ICEPT-HDP 2008, July 28-31, 2008, Shanghai, China. (NXP Semiconductor Best Paper Award)

  5. Shih-Ying Chiang, Shin-Yueh Yang, Chan-Yen Chou, Ming-Chih Yew, and Kuo-Ning Chiang, "Reliability Analysis of Copper Interconnections of System-in-Package Structure using Finite Element Method," Proceedings of International Conference on Electronic Packaging Technology and International Symposium on High Density Packaging, ICEPT-HDP 2008, July 28-31, 2008, Shanghai, China.

  6. Ming-Chih Yew, Chung-Jung Wu, Ching-Shun Huang, Mars Tsai, Dyi-Chung Hu, Wen-Kung Yang, and Kuo-Ning Chiang, "Trace Line Failure Analysis and Characterization of the Panel Base Package (PBPTM) Technology with Fan-Out Capability," Proceedings of the 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITherm 2008, pp. 862-869, May 28 -31, 2008, Florida, USA.

  7. Chan-Yen Chou, Tuan-Yu Hung, Ming-Chih Yew, Wen-Kun Yang, Dyi-Chung Hu, Mon-Chin Tsai, Ching-Shun Huang, and Kuo-Ning Chiang, "Investigation of Stress-buffer-enhanced Package Subjected to Board-level Drop Test," Proceedings of the 9th International conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSIME2008, pp. 372-377, April 20-23, 2008, Breisgau, Germany.

  8. Shih-Ying Chiang, Chan-Yan Chou, Ming-Chih Yew, and Kuo-Ning Chiang, "Reliability Analysis of Copper Interconnection in System-in-package Structure," Proceedings of the 9th International Conference on Electronics Materials and Packaging (EMAP2007), November 19-22, 2007, Korea.

  9. Ming-Chih Yew, Chan-Yen Chou, and Kuo-Ning Chiang, "Reliability Assessment for Solders with a Stress Buffer Layer using Ball Shear Strength Test and Board-level Finite Element Analysis," Proceedings of the 18th European Symposium Reliability of Electron Devices, Failure Physics and Analysis, ESREF2007, pp. 1658-1662, October 8-12, 2007, Arcachon, France.

  10. Ming-Chih Yew and Kuo-Ning Chiang, "A Study of Material Effects for the Panel Level Package (PLP) Technology," Proceedings of the 2nd International Microsystems, Packaging, Assembly and Circuits Technology conference, IMPACT2007, pp. 98-101, October 1-3, 2007, Taipei, Taiwan. (Best Student Paper Award)

  11. Hsiu-Ping Wei, Ming-Chih Yew, and Kuo-Ning Chiang, "FAILURE MODE AND THERMAL PERFORMANCE ANALYSIS OF STACKED PANEL LEVEL PACKAGE (PLP)," Proceedings of 2007 International Electronic Packaging Technical Conference and Exhibition, InterPACK 2007, pp. 693-701, July 8-12, 2007, Vancouver, Canada.

  12. Chan-Yen Chou, Chung-Jung Wu, Hsiu-Ping Wei, Ming-Chih Yew, Chien-Chia Chiu, and Kuo-Ning Chiang, "THERMAL MANAGEMENT ON HOT SPOT ELIMINATION / JUNCTION TEMPERATURE REDUCTION FOR HIGH POWER DENSITY SYSTEM IN PACKAGE STRUCTURE," Proceedings of 2007 International Electronic Packaging Technical Conference and Exhibition, InterPACK 2007, July 8-12, 2007, Vancouver, Canada.

  13. C. Y. Chou, C. J. Wu, H. P. Wei, M. C. Yew, C. C. Chiu, and K. N. Chiang, "Thermal Management on Hot Spot Elimination / Junction Temperature Reduction for High Power Density System in Package Structure," Proceedings of the 7th International Congress on Thermal Stresses, June 4-7, 2007, Taipei, Taiwan.

  14. Ming-Chih Yew, Hsiu-Ping Wei, Ching-Shun Huang, Dyi-Chung Hu, Wen-Kung Yang, and Kuo-Ning Chiang, "A Study of Failure Mechanism and Reliability Assessment for the Panel Level Package (PLP) Technology," Proceedings of the 8th International conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSIME2007, pp. 475-482, April 16-18, 2007, London, England.

  15. Hsiu-Ping Wei, Ming-Chih Yew, Wen-Kung Yang, and Kuo-Ning Chiang, "Reliability Analysis of a Package-on-Package Structure Using Novel WLCSP Technology with Fan-Out Capability," Proceedings of the 8th International Conference on Electronics Materials and Packaging (EMAP2006), pp. 164-170, Dec. 11-14, 2006, Hong Kong.

  16. Ming-Chih Yew, Shu-Ming Chang, and Kuo-Ning Chiang, "Reliability Analysis of a New Soft Joint Protection Technology Using in WLCSP," Proceedings of 2006 International Microsystems, Packaging, Assembly Conference Taiwan (IMPACT 2006), pp. 151-154, October 18-20, 2006, Grand Formosa Regent Taipei, Taiwan.

  17. M. C. Yew, C. Y. Chou, C. S. Huang, W. K. Yang, and K. N. Chiang, "The Solder on Rubber (SOR) Interconnection Design and Its Reliability Assessment Based on Shear Strength Test and Finite Element Analysis," Proceedings of the 17th European Symposium Reliability of Electron Devices, Failure Physics and Analysis, ESREF2006, pp. 1874-1879, October 3-6, 2006, Wuppertal, Germany.

  18. M. C. Yew, C. Yuan, C. N. Han, C. S. Huang, W. K. Yang and, K.N. Chiang, "Factorial Analysis of Chip-on-Metal WLCSP Technology with Fan-Out Capability," Proceedings of the 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA2006, pp. 223-228, July 3-7, 2006, Singapore.

  19. Cadmus Yuan, Chan-Yen Chou, Cheng Nan Han, Ming-Chih Yew, and Kuo-Ning Chiang, "12" Wafer to 8" Wafer Transformation Technique Using Novel Glass WLCSP Structure," Proceedings of IMAPS-Taiwan 2006 Technical Symposium,  June 28 - July 1, 2006, Taipei World Trade Center, Taipei, Taiwan.

  20. Ming-Chih Yew, Yu- Hua Chen, Wen-Kung Yang, and Kuo-Ning Chiang,"Using FEM-based Method for Sensitivity Design of Chip-in-Substrate-Package," Proceedings of IMAPS-Taiwan 2006 Technical Symposium,  June 28 - July 1, 2006, Taipei World Trade Center, Taipei, Taiwan.

  21. Ming-Chih Yew, Ching-Shun Huang, Wen-Kung Yang, and Kuo-Ning Chiang,"Reliability and Characterization of Novel WLCSP with Fan-Out Capability," Proceedings of IMAPS-Taiwan 2006 Technical Symposium,  June 28 - July 1, 2006, Taipei World Trade Center, Taipei, Taiwan.

  22. C. Yuan, G. Q. Zhang, C. S. Huang, C. H. Yu, C. C. Yang, W. K. Yang, M. C. Yew, C. Y. Chou, and K. N. Chiang, "Design, Experiment and Analysis of the Solder on Rubber (SOR) structure of WLCSP," Proceedings of the 7th International conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSIME2006, pp. 619-625, April 23-26, 2006, Como (Milano), Italy.

  23. C. Yuan, G. Q. Zhang, C. S. Huang, C. H. Yu, C. C. Yang, W. K. Yang, M. C. Yew, C. N. Han, and K. N. Chiang, "Design and Analysis of a novel fan-out WLCSP structure," Proceedings of the 7th International conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSIME2006, pp. 297-304, April 23-26, 2006, Como (Milano), Italy.

  24. Ming-Chih Yew, Chang-Ann Yuan, Yu- Hua Chen, Wen-Kung Yang, and Kuo-Ning Chiang, "Sensitivity Design of Chip-in-Substrate-Package Using DOE with Factorial Analysis Technology," Proceedings of the 7th International conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSIME2006, pp. 589-595, April 23-26, 2006, Como (Milano), Italy.

  25. C. Yuan, C. N. Han, C. Y. Chou, M. C. Yew, and K. N. Chiang, "Simulation of unzipping dsDNA mechanical response using Clustered Atomistic-Continuum Method." Proceedings of ICCES'05 International Conference, Dec. 1-6, 2005, Chennai, India.

  26. Ming-Chih Yew, Chang-Chun Lee, Shu-Ming Chang, and Kuo-Ning Chiang, "Reliability Analysis of a New Soft Joint Protection Technology Using in WLCSP," Proceeding of 2005 Taiwan ANSYS Users Conference, pp. 5-27~5-34, Oct. 23-25, 2005, Hualien, Taiwan.

  27. Ming-Chih Yew, Chang-Chun Lee, and Kuo-Ning Chiang, "A NOVEL WLCSP USING SOFT JOINT PROTECTION TECHNOLOGY," 2005 International Electronic Packaging Technical Conference and Exhibition, Proceedings of 2005 International Electronic Packaging Technical Conference and Exhibition, InterPACK 2005, July 17-22, 2005, San Francisco, CA, USA.

  28. Chang-Chun Lee, Hsin-Chih Liu, Ming-Chih Yew, and Kuo-Ning Chian, "3D Structure Design and Reliability Analysis of Wafer Level Package with Bubble-Like Stress Buffer Layer," Proceedings of the 9th Intersociety Conference on Thermal and Thermomechanical phenomena in Electronic Systems, ITherm 2004, pp. 317-324, Jun. 1-4, Las Vegas, USA.