Luke, Chien-Chia Chiu

邱建嘉

Ph.D. student

(Advisor: Dr. K. N. Chiang)

National Tsing Hua University

Dept. Power Mechanical Eng.

E-mail:  luke_ccc@webmail.pme.nthu.edu.tw,  d937709@oz.nthu.edu.tw

Room 407, Eng. Bldg. 1

Dept. Power Mechanical Eng.

National Tsing Hua University

101, Section 2 Kuang Fu Road, Hsinchu, Taiwan 300, Republic of China 

Tel: +886-35743716

　

Journal Paper:

  1. C. C. Chiu, C. C. Lee, T. L. Chou, C. C. Hsia, and K. N. Chiang, "Analysis of Cu/Low-k structure under back end of line process," Microelectronic Engineering, Vol. 85, Issue 10, pp. 2150-2154, 2008.
  2. C. C. Lee, T. L. Chou, C. C. Chiu, C. C. Hsia, and K. N. Chiang, "Cracking energy estimation of ultra low-k package using novel prediction approach combined with global–local modeling technique," Microelectronic Engineering, Vol. 85, Issue 10, pp. 2079-2084, 2008.
  3. Chien-Chia Chiu, H. H. Chang, C. C. Lee, C. C. Hsia and K.N. Chiang, "Reliability of Interfacial Adhesion in a Multi-Level Copper/Low-k Interconnect Structure," Microelectronics Reliability Vol. 47, 2007, pp. 1506–1511.
  4. Chien-Chia Chiu, Chung-Jung Wu,  Chih-Tang Peng,  Terry Ku, Kenny Cheng and Kuo-Ning Chiang, "Failure life prediction and factorial design of lead-free flip chip package," Transactions of the Chinese Institute of Engineers,Series A/Chung-kuo Kung Ch'eng Hsuch K'an, v 30, n 3, May, 2007, p 481-490
  5. Ming-Chih Yew, Chien-Chia Chiu, Shu-Ming Chang and Kuo-Ning Chiang, "A Novel Crack and Delamination Protection Mechanism for a WLCSP Using Soft Joint Technology," Soldering & Surface Mount Technology, Vol. 18, Issue 3, 2006, pp. 3-13.
  6. Liu, C. M., Lee, C. C., Ku, H. T., Chiu, C. C., and Chiang, K. N., “Interconnect Design and Thermal Stress/Strain Analysis of Flip Chip Packaging,” Key Engineering Materials, pp.521, 2006. (SCI/EI)
  7. Lee, C. C., Ku, H. T., Chiu, C. C., and Chiang, K. N., “A Novel Prediction Technique for Interfacial Crack Growth of Electronic Interconnect,” Key Engineering Materials, pp.533, 2006. (SCI/EI)

Conference Paper :

  1. Cjien-Chia Chiu , C.C. Lee and K.N. Chiang, "Study of Lamina Fracture of Cu/Low-k Interconnects Using the J-Integral Method," The 7th International Conference on Fracture and Strength of Solids (FEOFS 2007) 27-30 August 2007: Urumqi, CHINA
  2. Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Kuo-Ning Chiang, Terry Ku and Kenny Cheng, "LEAD-FREE FLIP CHIP PACKAGE RELIABILITY AND THE FINITE ELEMENT-FACTORIAL DESIGN METHODOLOGY," Proceedings of the IMAPS-Taiwan 2006 Technical Symposium, June 28 - July 1, 2006, Taipei World Trade Center, Taipei, Taiwan.
  3. Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Chan-Yen Chou and Kuo-Ning Chiang , "Reliability Impact of Highly Temperature-Dependent Underfill Material to the Lead-Free Flip Chip Package," EuroSimE2006 international Conference, 2006,in Como (Milano), Italy.
  4. Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Kuo-Ning Chiang, Terry Ku and Kenny Cheng "Reliability Analysis and Factorial Design of Lead-Free Flip Chip Package Using THE Finite Element Method",  Proceedings of IPACK2005, International Electric Packaging Technical Conference, July 17-22, San Francisco, California, USA
  5. Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Kuo-Ning Chiang, Terry Ku and Kenny Cheng "Reliability Assessment of Lead-Free Flip Chip Package Using Factorial Design Methodology", 2005 Taiwan ANSYS User Conference.
  6. Chien Chen Lee, Chang Chun Lee, Chien Chia Chiu, Kuo Ming Chen, Frank Kuo and Kou Ning Chiang, "Electromigration Characteristic of SnAg3.0Cu0.5 Flip-Chip Interconnection," 56th Electronic Components and Technology Conference (ECTC), May 30 - June 2, 2006 in San Diego, CA, USA
  7. Chang-Chun Lee, Chien-Chia Chiu, Kuo-Ning Chiang, "STABILITY OF J-INTEGRAL CALCULATION IN THE CRACK GROWTH
    OF COPPER/LOW-K STACKED STRUCTURES," ITherm 2006, May 30 - June 2, 2006 in San Diego, CA, USA
  8. Liu, C. M., Lee, C. C., Ku, H. T., Chiu, C. C., and Chiang, K. N., 2006, “Interconnect Design and Thermal Stress/Strain Analysis of Flip Chip Packaging,” International Conference on Experimental Mechanics 2006 (ICEM 2006), Jeju, Korea, Sep. 26-29.
  9. Lee, C. C., Ku, H. T., Chiu, C. C., and Chiang, K. N., 2006, “A Novel Prediction Technique for Interfacial Crack Growth of Electronic Interconnect,” International Conference on Experimental Mechanics 2006 (ICEM 2006), Jeju, Korea, Sep. 26-29.        

　

參與計畫：

  1. 台積電-清華大學合作研究計畫 (tsmc-NTHU Project)：
    Interfacial stress, Adhesion, Crack Propagation Simulation of Multilayer and Stacked Structure of Low-k Chip    （2006.01~2007.12）
  2. 工業技術研究院電子工業研究所專利搜尋 (2005.08 迄今)
  3. 2005  台積電-清華大學合作研究計畫 (tsmc-NTHU Project)：
    Interfacial stress, Adhesion, Crack Propagation Simulation of Multilayer and Stacked Structure of Low-k Chip    （2005.07~2005.12）
  4. 威盛電子-覆晶封裝結構可靠度之參數化有限元素分析與設計

　

專利 :

·         MING-CHIH YEW, CHIEN-CHIA CHIU, KUO-NING CHIANG, Taiwan patent no. I264103, "強化接地特性與內埋天線型之立體堆疊封裝結構", 2006.10.11