吳仲融 (Chung-Jung, Wu)

E-mail: d9533807@oz.nthu.edu.tw

Advanced Microsystem Packaging and Nano-Mechanics Research Lab.

　

Department of Power Mechanical Engineering,

National Tsing Hua University, Hsin Chu, Taiwan, R. O. C.

　

　

學歷 Education

  • 國立清華大學動力機械工程學系碩士, 指導教授: 江國寧 教授 (2004.09~2006.07)

M. S., Power Mechanical Engineering of Tsing Hua University, Taiwan. Adviser: Prof. K. N. Chiang (2004.09~2006.07)

  • 國立清華大學動力機械工程學系學士 (2000.09~2006.07)

B. S., Power Mechanical Engineering of Tsing Hua University, Taiwan (2000.09~2004.07)

  • 私立興國高級中學高中部 (1997.09~2000.07)

Hsing Kuo High School, Taiwan (1997.09~2000.07)

相關著作 Publication

期刊論文 Journal Papers:

  • C. J. Wu, M. C. Hsieh, C. C. Chiu, M. C. Yew, and K. N. Chiang, "Interfacial delamination investigation between copper bumps in 3D chip stacking package by using the modified virtual crack closure technique," Microelectronic Engineering, in press.  Link

  • C. J. Wu, M. C. Hsieh, and K. N. Chiang, "Strength evaluation of silicon die for 3D chip stacking packages using ABF as dielectric and barrier layer in through-silicon via," Microelectronic Engineering, vol. 87, pp. 505-509, 2010.  Link

  • C. J. Wu, C. Y. Chou, C. N. Han, and K. N. Chiang, "Estimation and Validation of Elastic Modulus of Carbon Nanotubes Using Nano-Scale Tensile and Vibrational Analysis," Computer Modeling in Engineering and Science, Vol. 41, No. 1, pp. 49-68, 2009. Link

  • M. C. Yew, C. C. A. Yuan, C. J. Wu, D. C. Hu, W. K. Yang, and Kuo-Ning Chiang, “Investigation of the Trace Line Failure Mechanism and Design of Flexible Wafer Level Packaging,” IEEE Transactions on Advanced Packaging, Volume, 32, No. 2, pp. 390-398, 2009.Link

  • K. N. Chiang, C. Y. Chou, C. J. Wu, C. J. Huang, and M. C. Yew, "Analytical solution for estimation of temperature-dependent material properties of metals using modified Morse potential," Computer Modeling in Engineering and Science, Vol. 37, No. 1, pp. 85-96, 2008.Link

  • C. C. Chiu, C. J. Wu, C. T. Peng, K. N. Chiang, T. Ku, and K. Cheng, "Failure life prediction and factorial design of lead-free flip chip package," Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers, Vol.30, No. 3, pp. 481-490, 2007. Link

  • K. N. Chiang, C. Y. Chou, and C. J. Wu, and C. A. Yuan, "Prediction of The Bulk Elastic Constant of Metals Using Atomic-Level Single-Lattice Analytical Method" Appl. Phys. Lett. 88, 171904, 2006. Link

碩士論文 Masters Dissertation:

  • 使用原子 – 連體力學法於奈米碳管之機械性質研究

Investigation of Carbon Nanotube Mechanical Properties Using Atomistic-Continuum Mechanics Method.

會議論文 Conference Papers:

  • C. J. Wu, M. C. Hsieh, and K. N. Chiang, "Delamination Investigation of Copper Bumps in 3D Chip Stacking Packages Using the Modified Virtual Crack Closure Technique," International Conference on Electronics Packaging, ICEP 2010, Sapporo, Japan, May 12-14, 2010.

  • C. J. Wu, M. C. Hsieh, C. C. Chiu, M. C. Yew, and K. N. Chiang, "Interfacial Delamination Investigation between Copper Bumps in 3D Chip Stacking Package by Using the Modified Virtual Crack Closure Technique," Materials for Advanced Metallization Conference, MAM 2010, Mechelen, Belgium, Mar. 7-10, 2010

  • C. J. Wu, M. C. Hsieh, and K. N. Chiang, "Die-Cracking Evaluation of Silicon Chip Covered with Polymer Film for 3D Chip Stacking Packages," International Conference on Electronics Packaging, ICEP 2009, Kyoto, Japan, Apr. 14-16, 2009.

  • C. J. Wu, M. C. Hsieh, and K. N. Chiang, "Strength Evaluation of Silicon Die for 3D Chip Stacking Packages Using ABF as Dielectric and Barrier Layer in Through-Silicon Via," Materials for Advanced Metallization Conference, MAM 2009, Grenoble, France, Mar. 8-11, 2009.

  • C. J. Wu, C. Y. Chou, C. N. Han, and K. N. Chiang, "Simulation and Validation of SWCNT Mechanical Properties," Taiwan ANSYS/Fluent Conference, 2008, Taipei, Taiwan.

  • H. P. Wei, M. C. Yew, C. J. Wu, and K. N. Chiang, "Reliability and Thermal Assessment of Stacked Chip-on-Metal Panel Based Package (PBPTM) with Fan-Out Capability," 2nd Electronics System-Integration Technology Conference, ESTC 2008, 01-04 September, London, England.

  • Ming-Chih Yew, Chung-Jung Wu and Kuo-Ning Chiang, "Trace Line Failure Analysis and Characterization of the Panel Base Package (PBPTM) Technology with Fan-Out Capability," Proceedings of the 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITherm 2008, pp. 862-869, May 28 -31, 2008, Florida, USA.

  • C. J. Wu, C. Y. Chou, C. N. Han, and K. N. Chiang, "Estimation and Validation of Elastic Modulus of Carbon Nanotubes Using Nano-Scale Tensile and Vibrational Analysis," International Conference on Computational & Experimental Engineering and Sciences 2008 (ICCES'08), 16-21 March, 2008, Honolulu, Hawaii, USA.

  • C. J. Huang, C. Y. Chou, C. J. Wu, and K. N. Chiang, "Investigation of the mechanical properties of nano-scale metallic crystal structural with point defects," European Nano System 2007 (ENS'07), December 3-4, 2007, Paris, France

  • C. Y. Chou, C. J. Wu, H. P. Wei, M. C. Yew, C. C. Chiu, and K. N. Chiang, "Thermal management on hot spot elimination / junction temperature reduction for high power density system in package structure," InterPACK 2007, July 8-12, 2007, Vancouver, BC, Canada.

  • Chan-Yen Chou, Chung-Jung Wu, Hsiu-Ping Wei, Ming-Chih Yew, Chien-Chia Chiu and Kuo-Ning Chiang, "Thermal Management on Hot Spot Elimination / Junction Temperature Reduction for High Power Density RF Multi-chip Module," Thermal Stress 2007, June 4-7, 2007, Taipei, Taiwan.

  • C. J. Wu, C. Y. Chou, C. N. Han, and K. N. Chiang, "Simulation and Validation of CNT Mechanical Properties – The Future Interconnection Material," Electronic Components and Technology Conference (ECTC 2007), May 30 - Jun. 1, Reno, USA.

  • Chung-Jung Wu, Chan-Yen Chou, Cheng-Nan Han, Kuo-Ning Chiang, "Numerical Simulation of the Mechanical Properties of Carbon Nanotube Using the Atomistic-Continuum Mechanics," European Nano System 2006, 14-15 December 2006, Paris, France.

  • Chung-Jung Wu, Chan-Yen Chou, Cheng-Nan Han, Kuo-Ning Chiang, “Investigation of Carbon Nanotube Mechanical Properties Using The Atomistic-Continuum Mechanics Method," NSTI Nanotech 2006, Boston, Massachusetts ( USA), 2006.

  • Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Chan-Yen Chou and Kuo-Ning Chiang , "Reliability Impact of Highly Temperature-Dependent Underfill Material to the Lead-Free Flip Chip Package," EuroSimE2006 international Conference, 2006,in Como (Milano), Italy.

  • Chan-Yen Chou, Cadmus Yuan, Chung-Jung Wu and Kuo -Ning Chiang, "Numerical Simulation of the Mechanical Properties of Nanoscale Metal Clusters Using the Atomistic-Continuum Mechanics Method," European Nano System 2005, 14-16 December 2005, Paris, France.

  • Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Kuo-Ning Chiang, Terry Ku and Kenny Cheng "Reliability Assessment of Lead-Free Flip Chip Package Using Factorial Design Methodology," Taiwan ANSYS User Conference, 2005

  • Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Kuo-Ning Chiang, Terry Ku and Kenny Cheng "Reliability Analysis and Factorial Design of Lead-Free Flip Chip Package Using THE Finite Element Method,"  Proceedings of IPACK2005, International Electric Packaging Technical Conference and Exhibition, San Francisco, California, USA, 2005

參與會議 Conference Attendance

  • 2010.05 – International Conference on Electronics Packaging, ICEP2010, Sapporo, Japan (Oral Presentation)

  • 2010.03 – Materials for Advanced Metallization Conference, MAM2010, Mechclen, Belgium (Oral Presentation)

  • 2009.04 – International Conference on Electronics Packaging, ICEP2009, Kyoto, Japan (Oral Presentation)

  • 2009.03 – Materials for Advanced Metallization Conference, MAM2009, Grenoble, France (Poster Presentation)

  • 2008.11 – Taiwan ANSYS/Fluent Conference, Taipei, Taiwan (Oral Presentation)

  • 2008.09 – 2nd Electronics System-Integration Technology Conference, ESTC 2008, London, England (Oral Presentation)

  • 2008.03 – International Conference on Computational & Experimental Engineering and Sciences 2008, ICCES'08, Honolulu, Hawaii, USA (Oral Presentation)

  • 2007.05 – Electronic Components and Technology Conference, ECTC 2007, Reno, USA (Oral Presentation)

  • 2006.12 – European Nano System 2006, ENS 2006, Paris, France (Oral Presentation)

  • 2006.05 – NSTI Nanotech 2006, Boston, USA (Poster Presentation)

  • 2005.12 – European Nano System 2005, ENS 2005, Paris, France (Oral Presentation)

參與計畫 Project

  • 工研院暨國立清華大學學界分包研究計畫 – 製程殘餘應力分析模型的開發 (2009.08~迄今)

    ITRI Project – Stress/Strain Analysis of MEMS Multi-Layer Structure Using Process Modeling Technology (2009.08~Now)

  • 工業技術研究院委託學術機構研究計畫 – 3DIC-SiP 介面可靠度分析與驗證 (2009.01~2009.12)

    ITRI Project – Validation and Analysis of the Interfacial Reliability of 3DIC-SiP (2009.01~2009.12)

  • 中華民國台灣薄膜電晶體液晶顯示器產業協會(工業技術研究院) – 複合凸塊專利搜尋 (2006.07~2009.11)

    Taiwan TFT LCD Association, TTLA (ITRI) – "Composite Bump" Patents Search (2006.07~2009.11)

  • 工業技術研究院委託學術機構研究計畫 – SiP疊孔結構介面應變能釋放率之驗證與應用 (2008.01~2008.12)

    ITRI Project – Validation and Application of Strain Energy Release Rate of the Interconnect Via in System-in-Packaging (2008.01~2008.12)

  • 工業技術研究院委託學術機構研究計畫 – SiP疊孔Interconnects介面破裂模型 (2007.01~2007.12)

    ITRI Project – Crack Model of the Interconnect Via in System-in-Packaging (2007.01~2007.12)

  • 育霈科技計畫合作案 – The Reliability Analysis of Novel Slide-able Cu Trace Wafer Level Chip Scale Package (2006.07~2007.03)

  • 行政院國家科學委員會奈米國家型科技計畫 – 利用單分子操控術進行DNA奈米劑量之創新研究(2005.09~2007.07)

  • 威盛電子 – 覆晶封裝結構可靠度之參數化有限元素分析與設計 (2004.09~2005.07)