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博士班

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張國欽

博士班2003年畢

畢業論文：

銅凸塊設計與金屬界層擴散成長對微電子元件可靠度影響研究

2. FAILURE PREDICTION IN PLASTIC BALL GRID ARRAY ELECTRONIC PACKAGING (PDF檔)

3. HYGROTHERMAL STRESS ANALYSIS OF PLASTIC BALL GRID ARRAY PACKAGE DURING SOLDER REFLOW (PDF檔)

4. 塑封球柵陣列電子構裝之界面脫層裂縫尖端應力強度因子分析(PDF檔)

5. Effect of Cu Stud on Solder Ball Shear Strength

6. Impact of Aging on Solder Ball Shear Strength

7. Solder Joint Reliability Analysis of a Wafer-level CSP Assembly with Cu Studs Formed on Solder Pads

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陳國明

博士班2003年畢

畢業論文：

微電子元件針測壓痕之深度預測及其對錫鉛凸塊電子遷移影響之研究

相關著作：

1. PBGA 與T²-BGA之共面性研究(PDF檔)

2. Impact of probing procedure on flip chip reliability

3. Thermal Resistance Analysis and Validation of Flip Chip BGA Packages

4. Developing an Analytic Methodology to Predict Probing Depth in Integrated Circuit Structures

5. 以解析法預測積體電路元件之針測壓痕深度

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林基正

博士班2003年畢
　

畢業論文：

微電子元件封裝可靠度暨散熱特性之設計分析與驗證

2. A study of Factors Affecting Solder Joint Fatigue Life ofThermally Enhanced Ball Grid Array Assembly

3. Thermal/mechanical analysis of novel C-TSOP using nonlinear FEM method

4. Design and Analysis of Ceramic-TSOP Package

5. A Full-Scale 3D Finite Element Analysis for No-underfill Flip Chip Package

6. Investigation of Thermal Effect of Packaged CMOS Compatible Pressure Sensor

7. Design and Analysis of Wafer-Level CSP with Double-Pad-Structure

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劉昌明

畢業論文：

電訊接點配置、幾何及製造參數對微電子元件可靠度影響之研究

相關著作：

Solder Shape Design and Thermal Stress/Strain Analysis of Flip Chip Packaging Using Hybrid Method (PDF檔)
Analysis of Reflow Geometry for TheHybrid-Pad-Shapes System of Ball Grid Array Packages(PDF檔)
Solder Reflow Prediction of Hybrid Pad Packaging System (PDF檔)
Pad Design and Reliability Analysis for Flip Chip Packaging.
Design and Thermal Stress/Strain Analysis of Cast-In Dry Liner.
Solder Bumps Layout Design and Reliability Enhancement of Wafer Level Packaging.

參與計畫：

鑫成科技-覆晶構裝設計準則建置計畫
2000/03-2001/02
華擎計畫
2001/04-2002/03 2002/08-2003/07
威盛電子-覆晶封裝之結構設計與可靠度測試
裕沛科技公司WLCSP與WLPC開發及驗證
工研院能資所燃料電池計畫

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袁長安

博士班2005年畢

畢業論文：

利用叢集原子-連體理論研究奈米結構力學行為

Homepage: http://ccca.nctu.edu.tw/~cayuan/cayuan/index.htm

相關著作：

Journal Paper

1. K. N. Chiang and C. A. Yuan, "An Overview of Solder Bump Shape Prediction Algorithms with Validations", IEEE Transactions on Advanced Packaging, Vol.24, No.2, pp.158-162, May, 2001 (SCI/EI)

2. C. A. Yuan and K. N. Chiang, " Micro to Macro Thermo-Mechanical Simulation of Wafer Level Packaging," ASME trans. on Journal of Electronic Packaging, vol 125, no. 4, pp. 576-581, Dec., 2003(SCI/EI)

Conference Paper

1. Yuan, C. A. and Chiang, K. N.,"Micro to Macro Thermo-Mechanical Simulation of Wafer Level Packaging", EuroSimE2001 Conference (IEEE,EI), April 9-11 2001, Paris

2. 袁長安、林基正、劉昌明、張國欽、江國寧，「微機電/電子構裝參數分析之人機介面」，2001 Taiwan User Conf., 翡翠灣，台北，台灣。

3. Yuan, C. A., Liu, H., Sun, M. H., Chiang, K. N., "Design, analysis and validation of vertical probing technology," EuroSimE2003 international Conference, 2003, Aix-en-Provence, France.

4. Yuan, C. A. and Chiang, K. N., "Investigation of dsDNA stretching meso-mechanics using finite Element Method”, 2004 Nanotechnology Conference, March 7-11, 2004, Boston, Massachusetts, U.S.A.

5. Yuan, C. A. and Chiang, K. N., "Investigation of dsDNA stretching meso-mechanics using LS-DYNA", 2004 LSTC User's Conf.,Dearbone,DI, U.S.A.

6. Yuan, C. A., Han, C. N. and Chiang, K. N., “Design and Analysis of Novel WLCSP Structure”, EuroSIME2004 International Conference, May 9-May 12, 2004, Brussels, Belgium.

專利（已申請）：

晶圓級測試卡之探針結構(TW)
具複數個接觸單元之電訊測試組件結構 (TW,公告號516150)
可重複使用之檢測結構(TW)

參與計畫：

華擎計畫
2001/04-2002/03
裕沛科技公司-WLCSP與WLPC開發及驗證

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彭治棠

博士班2005年畢

畢業論文：

先進微系統封裝之結構可靠度極為波訊號響應之設計、分析與實驗驗證

Homepage: d907710

相關著作：

Parametric Design and Reliability Analysis of Wire Interconnect Technology Wafer Level Packaging, ASME Transaction of Electronic Package, Vol.124, No. 3, pp. 234-239, Sep. 2002
Parametric Reliability Analysis of No-Underfill Flip Chip Package, IEEE Transactions on Components and Packaging Technologies, Vol. 24, No. 4, pp. 635-640, Dec. 2001
Reliability Analysis and Design for the Fine-pitch Flip Chip BGA Packaging, IEEE Transactions on Component and Packaging Technologies
Analysis and Validation of Thermal and Packaging Effects of a Piezoresistive Pressure Sensor, Journal of the Chinese Institute of Engineers (JCIE)
Performance and Package Effect of a Novel Piezoresistive Pressure Sensor Fabricated by Front-Side Etching Technology, Sensor and Actuator Journal (SNA)
Experimental Characterization and Mechanical Behavior Analysis of Intermetallic Compounds of Sn-3.5Ag Led-free Solder Bump with Ti/Cu/Ni UBM Copper Chip, Journal of Microelectronics Reliability
Overview of Multilayered Thin Film Theories for MEMS and Electronic Packaging Applications, 8th Intersociety Conference on Thermal and Thermommechanical phenomena in Electronic Systems, pp. 1058-1065, May 30-Jun. 1, 2002, San Diego, CA, United States
Investigation of Thermal Effect of Packaged CMOS Compatible Pressure Sensor, 2002 ASME International Mechanical Engineering Congress and Exposition, pp. 505-512, Nov. 17-22, 2002, New Orleans, LA, United States
The Reliability Analysis and Structure Design for the Fine Pitch Flip Chip BGA Package, 4th International Conference on Thermal & Mechanical Simulation and Experiments in Microelectronics and Microsystems, pp. 413-420, Mar. 30-Apr. 2, 2003, Aix-en-Provence, France
Analysis and Validation of Sensing Sensetivity of a Piezoresistive Pressure Sensor, 2003 International Electronic Packaging Technical Conference and Exhibition, pp. 225-231, Jul 6-11, 2003, Haui, HI, United States
A Novel Silicon Base Piezoresistive Pressure Sensor Using Front Side Etching Process, pp. 79-86, 2003 ASME International Mechanical Engineering Congress, Nov 15-21 2003, Washington, DC, United States
Design and Analysis of the CMOS Compatible Pressure Sensor Using Flip Chip and Flex Circuit Board Technologies, pp. 43-49, 2003 ASME International Mechanical Engineering Congress, Nov 15-21 2003, Washington, DC, United States
Design, Fabrication and Comparison of Lead-Free/Eutectic Solder Joint Reliability of Flip Chip Package, 5th international conference on thermal, mechanical and thermo-mechanical simulation and experiments in micro-electronics and icro-systems, pp. 149-156, Brussels, Belgium, May 10-12, 2004
Experimental Characterization and Mechanical Behavior Analysis on Intermetallic Compounds of 96.5Sn-3.5Ag and 63Sn-37Pb Solder Bump with Ti-Cu-Ni UBM on Copper Chip, 54th Electronic Components and Technology Conference, Las Vegas, United States
Reliability Analysis and Factorial Design of Lead-Free Flip Chip Package Using THE Finite Element Method, Proceedings of IPACK2005, International Electric Packaging Technical Conference and Exhibition, July 17-22, San Francisco, California, USA
Investigation of Local-Strain Effect of the Nano-Scale Triple Gate Si/SiGe and SiNx/Si Stacking MOS Transistor.” NSTI Nanotechnology Conference, May 8-12, 2005, Anaheim, California, USA

參與計畫：

樺晶科技公司-新型微壓力感測器研發與製造
威盛電子-覆晶封裝之結構設計與可靠度測試
威盛電子- a. 無鉛銲錫應用於覆晶封裝之結構設計與可靠度測試 b.無鉛銲錫之金屬界層成長與力學強度測試
威盛電子-覆晶封裝結構可靠度之參數化有限元素分析與設計
台灣積體電路公司-奈米級銅導線製程線路之有限單元參數化分析
工業技術研究院電子工程研究所_構裝製程技術組-專利工程師

專利：

低熱應力與高靈敏度點對點接合之微感測器結構（中華民國專利，發明第一六五四二八號）
矽材壓力微感測元件及其製造方法（中華民國專利，公告號500916)

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林俊德

博士班2006年畢

畢業論文:

使用原子連體力學於奈米等級單晶IV-A族之機械性質研究

相關著作：

Journal Paper

Chiang, K. N., Chang C. W. and Lin C. T., “Process Modeling and Thermal/Mechanical Behavior of ACA/ACF Type Flip-Chip Package,” TRANSATIONS of the ASME, Journal of Electronic Package, Vol. 123, pp. 331-337, 2001.

Lin, C. T. and Chiang, K. N., “Reliability Analysis of Flip Chip Packages Using the Contact Finite Element Method,” Journal of the Chinese Institute of Engineers, Vol. 27, No. 2, pp.165-172, 2004.

Conference Papers

Chiang, K.N. Chang C. W. and C. T. Lin, “Process and Reliability Simulation of Flip Chip using ACF", Proceeding of EPTC 2000 (IEEE, EI), pp. 110-116, Dec. 2000, Singapore.

Lin, C. T. and Chiang, K. N., "Reliability Analysis of Flip Chip Packages Using the Contact Finite Element Method", Published (CD-ROM) at Annual Meeting of CSME, Nov. 8, 2001, Taipei.

Peng, C. T., Lin, J. G., Lin, C. T and Chiang, K. N., "Investigation of Thermal Effect of Packaged CMOS Compatible Pressure Sensor", Published at 2002 ASME Intl. Mechanical Engineering Congress and Exposition, Symposium on Microelectronic Manufacturing, Reliability, and Quality Assurance Testing, Nov. 17-22, 2002, New Orleans, USA.

Lin, C. T., Peng, C. T., Lin, J. C. and Chiang, K. N., “Analysis and Validation of Sensing Sensitivity of a Piezoresistive Pressure Sensor”, Published at InterPACK2003 (IEEE/ASME), June 30 – July 5, Hawaii, USA.

J. Y. Chen, C. T. Lin, W. C. Liao, H. C. Su, C. H. Ysai and K. N. Chiang, “A New Nano-Probe Using Micro Assembly Transfer”, Published at 3rd Cross-Strait Workshop on Nano Science & Technology, April 27 – 29, 2004, HuaLian, Taiwan.

C.T. Lin, W.C. Liao, J.Y. Chen, H.C. Su and K.N. Chiang , “Design and Analysis of Nano-Probe of AFM Using Large Deflection Theory “, 3rd Cross-Strait Workshop on Nano Science & Technology, April 27 – 29, 2004, HuaLian, Taiwan.

Chen, J. Y., Lin, C. T., Liao, W. C., Su, H. C., Tsai, C. H. and Chiang, K. N., “A New Nano-Probe Using Micro Assembly Transfer”, Published at First International Nano Bio-Packaging Workshop, March 22-23, 2004, Atlanta.

C. T. Lin, W. C. Liao, J. Y. Chen, H. C. Su and K. N. Chiang, “Design and Analysis of a Nano-Probe for the AFM based on the Small/Large Deflection Theory,” Published at 2004 ASME Intl. Mechanical Engineering Congress and Exposition, Nov. 13-19, 2004, Anaheim, USA.

W. C. Liao, C. T. Lin and K. N. Chiang, “Experiment Validation of a Nano-Probe for the AFM based on the Large Deflection Theory,” Published (CD-ROM) at Annual Meeting of CSME, Nov. 11, 2004, KaoHsiung.

C. T. Lin and K. N. Chiang,” Thermal and Mechanical Responses of Thermomechanical Microprobe for High Density Storage Technology,” published at Microelectronics, MEMS, and Nanotechnology 2005 (SPIE), Brisbane, Australia, Dec. 11–14 2005.

C. T. Lin and K. N. Chiang,”Investigation of Nano-Scale Single Crystal Silicon Using the Atomistic-Continuum Mechanics with Stillinger-Weber Potential Function,” published at NanoSingapore 2006 (IEEE), Singapore, Jan. 10-13, 2006.

參與計畫：

l 樺晶科技公司-新型微壓力感測器研發與製造

l 華擎計畫-引擎汽缸熱傳分析與設計 (2001/04-2002/03)

l 工業技術研究院電子工程研究所構裝製程技術組-專利工程師

l 工業技術研究院電子工程研究所-自主性前瞻計畫-原子力顯微鏡之奈米探針設計與分析

專利：

低熱應力與高靈敏度點對點接合之微感測器結構（中華民國專利，發明第一六五四二八號）
矽材壓力微感測元件及其製造方法（中華民國專利，公告號500916）
具有光波導之掃描探針式/進場光學式顯微鏡用之探針（中華民國專利，證號I237276）

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李昌駿

博士班2006年畢

畢業論文:

以介面破裂成長之預測法研究微電子元件之可靠度

相關著作：

Journal Papers

1. Lee, C. C., Chiang, K. N., Chen, W. K., and Chen, R. S., “Design and Analysis of Gasket Sealing of Cylinder Head under Engine Operation Conditions,” Finite Elements in Analysis and Design, Vol. 41, No. 11-12, pp. 1160-1174, Jun. 2005.

2. Lee, C. C. and Chiang, K. N., “Design and Reliability Analysis of a Novel Wafer Level Package with Stress Buffer Mechanism,” Accepted and to be published at Journal of the Chinese Institute of Engineers, 2005.

3. Lee, C. C., Liu, H. C., and Chiang, K. N., "3D Structure Design and Reliability Analysis of Wafer Level Package with Stress Buffer Mechanism," Accepted and to be published at IEEE Transactions on Component and Packaging Technologies, 2006.

4. Yen-Fu Su, Shin-Yueh Yang, Tuan-Yu Hung, Chang-Chun Lee, and Kuo-Ning Chiang, "Light degradation test and design of thermal performance forhigh-power light-emitting diodes," Microelectronics Reliability, in press

Conference Papers

1. Lee, C. C., Chiang, K. N., 2003, “Design and Reliability Analysis of Wafer Level Package with Bubble-Like Buffer Layer,”2003 International Electronic Packaging Technical Conference and Exhibition, Vol. 2, pp.813-818, Maui, Hawaii, USA, Jul. 6-11.

2. Peng, C. T., Lee, C. C., and Chiang, K. N., 2003, “Design and Analysis of the CMOS Compatible Pressure Sensor Using Flip Chip and Flex Circuit Board Technologies,” ASME International Mechanical Engineering Congress & Exposition, Vol. 3, pp.43-49, Washington, D.C., USA, Nov. 15-21.

3. Lee, C. C., Chiang, K. N., Chen, W. K., and Chen, R. S., 2003, “Design and Analysis of Temperature Distribution for 2.0L Cylinder Head in Engine Operation,” The 20^th National Conference on Mechanical Engineering, Vol. 3, pp.1189-1196, CSME, Taipei, Taiwan, Dec. 5-6.

4. Lee, C. C., Chiang, K. N., Chen, W. K., and Chen, R. S., 2003, “Design and Analysis of Gasket Sealing for Cylinder Head in 2.0L Engine Operation,” Paper #G225, The 27^th Conference on Theoretical and Applied Mechanics, Tainan, Taiwan, Dec. 12-13.

5. Lee, C. C., Liu, H. C., and Chiang, K. N., 2004, “3D Structure Design and Reliability Analysis of Wafer Level Package with Bubble-Like Stress Buffer Layer,” 9^th Intersociety Conference on Thermal and Thermomechanical phenomena in Electronic Systems (ITHERM 2004), Las Vegas, USA, Jun. 1-4.

6. Lee, C. C., Chang, S. M., and Chiang, K. N., 2004, “Design of Double Layer WLCSP Using DOE with Factorial Analysis Technology,” 6th IEEE Electronics Packaging Technology Conference (EPTC 2004), pp.776-781, Singapore, Dec. 8-10.

7. Liu, C. M., Lee, C. C., and Chiang, K. N., 2005, “Solder Joints Layout Design and Reliability Enhancement of Wafer Level Packaging,”6th IEEE EuroSimE2005 conference, pp.234-241, Berlin, Germany, Apr. 18-20.

8. Lee, Chien Chen, Lee, Chang Chun, and Chiang, Kou Ning, 2005,“Thermal Performance and Solder Joint Reliability for Board Level Assembly of Modified Leadframe Module,”6th IEEE EuroSimE2005 conference, pp.553-558, Berlin, Germany, Apr. 18-20.

9. Lee, Chang Chun, Lee, Chien Chen, Cheng, Chih Yuan, and Chiang, Kou Ning, 2005,“Robust Design for the Reliability Optimization of WLCSP Using Response Surface Methodology,”IMAPS-TAIWAN 2005 International Technical Symposium, pp.209-214, Taipei, Taiwan, Jun. 23-25.

參與計畫：

1. 裕沛科技/清華大學合作案：Wafer Probe card與Wafer Level Packaging研發計畫（2001/07~2001/12）.

2. 華擎機械工業股份有限公司委託學術機構研究計畫：汽缸頭結構最佳化分析研究轉委託計畫（2002/08~2003/07）.

3. 工業技術研究院電子工業研究所專利搜尋：COG相關結構、製程專利（2003/01~2003/06）.

4. 工業技術研究院電子工業研究所專利搜尋：Wafer Probe card相關結構、製程專利（2003/07~2003/12）.

5. 工業技術研究院電子工業研究所專利搜尋：COG、NCP模組相關專利（2004/01~迄今）.

6. 工業技術研究院電子工業研究所自主性前瞻計畫（微液相成型混合理論應用於晶圓級封裝可靠性與微結構體自動組裝研發）：5X/16X Product Design and Development Procedure，WLCSP參數化分析與設計開發（2003/05~2004/12）.

7.台積電-清華大學合作研究計畫：
Interfacial stress, Adhesion, Crack Propagation Simulation of Multilayer and Stacked Structure of Low-k Chip（2005/01~迄今）

專利：

1. 楊文焜, 楊文彬, 王誌榮, 林明輝, 孫文彬, 吳皓然, 江國寧, 李昌駿, 廖啟銘,袁長安,
“晶圓級測試卡之探針結構” 本案獲台灣發明專利, 公告號：531,645, 證書號：177,789, May 11, 2003.

2. 袁長安, 李昌駿, 廖啟銘, 江國寧,
“具複數個接觸單元之電訊測試組件結構” 本案獲台灣發明專利, 公告號：516,150, 證書號：170,790, Jan. 1, 2003.

3. 李昌駿, 江國寧, 韓政男, 游明志,
“堆疊多重封裝單元之晶圓級系統封裝結構” 本案獲台灣發明專利, 公告號：I 233,192, 證書號：I 233,192, May 21, 2005.

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李建成

博士班2006年畢

畢業論文:

錫銀銅覆晶微接點暨鋁導線外加機械應力之電遷移研究

相關著作

Paper

* Kou Ning Chiang, Chien Chen Lee, Kuo Ming Chen, and Chang Chun Lee “Current crowding-induced electromigration study in SnAg3.0Cu0.5 micro-bump”, Accepted and to be published at Journal of Applied Physics Letters 2006

* Chien Chen Lee, Kuo Ming Chen, Chang Chun Lee, Frank Kuo, and Kou Ning Chiang, “Characteristics of SnAg3.0Cu0.5 Flip Chip Solder Bump Electromigration”, Accepted and to be published at The 56th Electronic Components and Technology Conference, May 30 - June 2, 2006, San Diego, California USA.

* Chien Chen Lee, Kuo Ming Chen, Frank Kuo, and Kou Ning Chiang, “Electromigration Study of SnAg3.0Cu0.5 Flip Chip Solder Bumps”, Accepted and to be published at The 2006 Pan Pacific Microelectronics Symposium, Jan. 17 - 19, 2006, Hawaii, USA.

* Chang Chun Lee, Chien Chen, Lee, Chin-Yuan, Cheng, Kuo Ning Chiang, “Robust Design for the Reliability Optimization of WLCSP Using Response Surface Methodology”, Published at The IMAPS-Taiwan 2005 Technical Symposium, June 23 - 25, 2005, Taipei, Taiwan

* Chien Chen Lee, Chang Chun Lee, Chip Tang Peng and Kou Ning Chiang, “Thermal Performance and Solder Joint Reliability for Board Level Assembly of Modified Leadframe Module”, Published at The 6th IEEE EuroSimE international conference (IEEE/ASME), April 18-20, 2005, Berlin, Germany

* Chien Chen Lee and Kou Ning Chiang, “RF Substrate Via Relative Issue Discussion - Via and Ni/Au Surface Layer Crack”, Published at The 7th VLSI Packaging Workshop of Japan (IEEE/CMPT), Nov. 30 - Dec. 2, 2004, Kyoto, Japan.

Patent

* Taiwan Patent No. 204,164
* Taiwan Patent No. 204,838
* Taiwan Patent No. I227,051
* Taiwan Patent No. I236,124
* Taiwan Patent Application No. 94139456
* Taiwan Patent Application No. 94138242
* Taiwan Patent Application No. 93130206
* China Patent Application No. 200410086160.9
* China Patent Application No. 200410054496.7
* China Patent Application No. 200410038470.3
* US Patent Application No. 11/023,749
* US Patent Application No. 10/964,542
* US Patent Application No. 10/922,422
　

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顧曉東

博士班 2007年畢

畢業論文：

機械應力引致類比元件及金氧半場效電晶體電性特性漂移與變動之研究

相關著作

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韓政男

博士班2009年畢

E-mail:d927715@oz.nthu.edu.tw

Homepage: d927715

畢業論文：

利用原子-連體力學理論探討生物奈米結構力學行為

相關著作:

C. A. Yuan, C. N. Han, M. C. Yew, C. Y. Chou and K. N. Chiang, "Design, Analysis and Development of Novel Three-Dimensional Stacking WLCSP," accepted by IEEE Transaction of Advanced Packaging.
C. A. Yuan, C. N. Han and K. N. Chiang , “Design and Analysis of Novel WLCSP Structure”, EuroSIME2004 International Conference, May 9-May 12, 2004, Brussels, Belgium.
C. A. Yuan, C. N. Han and K. N. Chiang, "Atomistic to Continuum Mechanical Investigation of ssDNA and dsDNA using Transient Finite Element Method," Inter-Pacific Workshop on Nanoscience and Nanotechnology, Nov. 22-Nov. 24, City University of Hong Kong, Hong Kong SAR.

參與計畫:

裕沛科技公司-WLCSP與WLPC開發及驗證

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游明志

博士班2009年畢

E-mail: jasonyew@webmail.pme.nthu.edu.tw

My Homepage: d923768(more detail about me)

畢業論文：

先進微電子封裝技術之設計.結構可靠度分析與電遷移效應評估

Main Projects:

清華大學/育霈科技計畫合作案, 新型可堆疊式系統級封裝技術之產品可靠度與散熱特性分析 (The Reliability Assessment and Thermal Performance Evaluation for Novel Stackable System-in-Package Technology), 2008.03 迄今
工業技術研究院電子與光電工業研究所專利搜尋, 三維堆疊式晶片發展技術, 2008.02 迄今
清華大學/育霈科技計畫合作案, 新型可滑動之彎曲導線式晶圓級晶片尺寸構裝之可靠度分析-Ⅲ (The Reliability Analysis of Novel Slide-able Cu Trace Wafer Level Chip Scale Package Ⅲ), 2007.03~2008.02
清華大學/育霈科技計畫合作案, 新型可滑動之彎曲導線式晶圓級晶片尺寸構裝之可靠度分析-Ⅱ (The Reliability Analysis of Novel Slide-able Cu Trace Wafer Level Chip Scale Package Ⅱ), 2006.03~2007.02
清華大學/育霈科技計畫合作案, 新型可滑動之彎曲導線式晶圓級晶片尺寸構裝之可靠度分析-Ⅰ The Reliability Analysis of Novel Slide-able Cu Trace Wafer Level Chip Scale PackageⅠ), 2005.06~2006.02
台積電/清華大學從事半導體合作研究計畫, Interfacial stress, adhesion, crack propagation simulation of multilayer and stacked structure of low-k chip, 2005.02~2006.01
工業技術研究院電子工業研究所自主性前瞻計畫, 5X/16X Product Design and Development Procedure, 2004.01~2004.12
工業技術研究院電子工業研究所專利搜尋, Stretchable Circuit 相關結構、設計, 2005.08~2008.02

Issued Patents:

Ming-Chih Yew, Chien-Chia Chiu, Kuo-Ning Chiang, and Wen-Kun Yang, US patent published no. 20080142941. "3D ELECTRONIC PACKAGING STRUCTURE WITH ENHANCED GROUNDING PERFORMANCE AND EMBEDDED ANTENNA," published on June 19, 2008
Ming-Chih Yew, Chang-Ann Yuan, Chan-Yen Chou, and Kuo-Ning Chiang, US patent published no. 20070296065, "3D electronic packaging structure having a conductive support substrate", published on December 27, 2007
Ming-Chih Yew, Chang-Ann Yuan, Chan-Yen Chou, and Kuo-Ning Chiang, Taiwan patent no. I269460, "A 3D electronic packaging structure using conductive substrate", 2006.12.21
Ming-Chih Yew, Chien-Chia Chiu, and Kuo-Ning Chiang, Taiwan patent no. I264103, "A 3D electronic packaging structure with enhanced grounding performance and embedded antenna", 2006.10.11
Chang-Chun Lee, Kuo-Ning Chiang, Cheng-Nan Han, and Ming-Chih Yew, Taiwan patent no. I233192, "The wafer level structure of system packaging with stacked packaging units", 2005.05.21

Journal papers:

Ming-Chih Yew, Chan-Yen Chou, and Kuo-Ning Chiang, "Reliability Assessment for Solders with a Stress Buffer Layer using Ball Shear Strength Test and Board-level Finite Element Analysis," Journal of Microelectronics Reliability, Vol. 47, pp. 1658-1662, 2007.
M. C. Yew, C. Y. Chou, C. S. Huang, W. K. Yang, and K. N. Chiang, "The Solder on Rubber (SOR) Interconnection Design and Its Reliability Assessment Based on Shear Strength Test and Finite Element Analysis," Journal of Microelectronics Reliability, Vol. 46, pp. 1874-1879, 2006.
Ming-Chih Yew, Chien-Chia Chiu, Shu-Ming Chang, and Kuo-Ning Chiang, "A Novel Crack and Delamination Protection Mechanism for a WLCSP Using Soft Joint Technology," Soldering & Surface Mount Technology, Vol. 18, Issue 3, pp. 3-13, 2006.
C. A. Yuan, C. N. Han, M. C. Yew, C. Y. Chou, and K. N. Chiang, "Design, Analysis and Development of Novel Three-Dimensional Stacking WLCSP," IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 28, NO. 3, pp. 387-396, AUGUST 2005.

Conference papers:

(Provided in my personal website)

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邱建嘉

博士班2009年畢

E-mail: d937709@oz.nthu.edu.tw

Homepage: d937709

畢業論文：

多層內導線連接結構脫層與機械應力導致載子遷移率改變之研究

相關著作 :

	C. C. Chiu, C. C. Lee, T. L. Chou, C. C. Hsia, and K. N. Chiang, "Analysis of Cu/Low-k structure under back end of line process," Microelectronic Engineering, Vol. 85, Issue 10, pp. 2150-2154, 2008.
	C. C. Lee, T. L. Chou, C. C. Chiu, C. C. Hsia, and K. N. Chiang, "Cracking energy estimation of ultra low-k package using novel prediction approach combined with global–local modeling technique," Microelectronic Engineering, Vol. 85, Issue 10, pp. 2079-2084, 2008.
	Chien-Chia Chiu, H. H. Chang, C. C. Lee, C. C. Hsia and K.N. Chiang, "Reliability of Interfacial Adhesion in a Multi-Level Copper/Low-k Interconnect Structure," Microelectronics Reliability Vol. 47, 2007, pp. 1506–1511.
	Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Chan-Yen Chou and Kuo-Ning Chiang , "Reliability Impact of Highly Temperature-Dependent Underfill Material to the Lead-Free Flip Chip Package," EuroSimE2006 international Conference, 2006,in Como (Milano), Italy.
	Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Kuo-Ning Chiang, Terry Ku and Kenny Cheng, "LEAD-FREE FLIP CHIP PACKAGE RELIABILITY AND THE FINITE ELEMENT-FACTORIAL DESIGN METHODOLOGY," Proceedings of the IMAPS-Taiwan 2006 Technical Symposium, June 28 - July 1, 2006, Taipei World Trade Center, Taipei, Taiwan.
	Chien Chen Lee, Chang Chun Lee, Chien Chia Chiu, Kuo Ming Chen, Frank Kuo and Kou Ning Chiang, "Electromigration Characteristic of SnAg3.0Cu0.5 Flip-Chip Interconnection," 56th Electronic Components and Technology Conference (ECTC), May 30 - June 2, 2006 in San Diego, CA, USA
	Chang-Chun Lee, Chien-Chia Chiu, Kuo-Ning Chiang, "STABILITY OF J-INTEGRAL CALCULATION IN THE CRACK GROWTH OF COPPER/LOW-K STACKED STRUCTURES," ITherm 2006, May 30 - June 2, 2006 in San Diego, CA, USA
	Liu, C. M., Lee, C. C., Ku, H. T., Chiu, C. C., and Chiang, K. N., 2006, “Interconnect Design and Thermal Stress/Strain Analysis of Flip Chip Packaging,” International Conference on Experimental Mechanics 2006 (ICEM 2006), Jeju, Korea, Sep. 26-29.
	Lee, C. C., Ku, H. T., Chiu, C. C., and Chiang, K. N., 2006, “A Novel Prediction Technique for Interfacial Crack Growth of Electronic Interconnect,” International Conference on Experimental Mechanics 2006 (ICEM 2006), Jeju, Korea, Sep. 26-29.
	Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Kuo-Ning Chiang, Terry Ku and Kenny Cheng "Reliability Assessment of Lead-Free Flip Chip Package Using Factorial Design Methodology", Taiwan ANSYS User Conference, 2005
	Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Kuo-Ning Chiang, Terry Ku and Kenny Cheng "Reliability Analysis and Factorial Design of Lead-Free Flip Chip Package Using THE Finite Element Method", Proceedings of IPACK2005, International Electric Packaging Technical Conference and Exhibition, July 17-22, San Francisco, California, USA
	Ming-Chih Yew, Chien-Chia Chiu, Shu-Ming Chang and Kuo-Ning Chiang, "A Novel Crack and Delamination Protection Mechanism for a WLCSP Using Soft Joint Technology," Soldering & Surface Mount Technology, Vol. 18, Issue 3, 2006, pp. 3-13.
	Liu, C. M., Lee, C. C., Ku, H. T., Chiu, C. C., and Chiang, K. N., “Interconnect Design and Thermal Stress/Strain Analysis of Flip Chip Packaging,” Key Engineering Materials, pp.521, 2006. (SCI/EI)
	Lee, C. C., Ku, H. T., Chiu, C. C., and Chiang, K. N., “A Novel Prediction Technique for Interfacial Crack Growth of Electronic Interconnect,” Key Engineering Materials, pp.533, 2006. (SCI/EI)

參與計畫：

	台積電-清華大學合作研究計畫： Interfacial stress, Adhesion, Crack Propagation Simulation of Multilayer and Stacked Structure of Low-k Chip（2005.07~迄今）
	工業技術研究院電子工業研究所專利搜尋 (2005.08 迄今)
	威盛電子-覆晶封裝結構可靠度之參數化有限元素分析與設計 (2004.09~2005.07)

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周展延

博士班2009年畢

E-mail: d947704@oz.nthu.edu.tw

Homepage: d947704

畢業論文：

晶圓級封裝掉落衝擊動態分析及其衝擊壽命預測理論研究

相關著作

	C. J. Wu, C. Y. Chou, C. N. Han, and K. N. Chiang, "Estimation and Validation of Elastic Modulus of Carbon Nanotubes Using Nano-Scale Tensile and Vibrational Analysis," Computer Modeling in Engineering and Science, Vol. 41, No. 1, pp. 49-68, 2009.
	K. N. Chiang, C. Y. Chou, C. J. Wu, C. J. Huang, and M. C. Yew, "Analytical solution for estimation of temperature-dependent material properties of metals using modified Morse potential," Computer Modeling in Engineering and Science, Vol. 37, pp. 85-96, 2008.
	S. Y. Chiang, S. Y. Yang, C. Y. Chou, M. C. Yew, and K. N. Chiang, "Reliability Analysis of Copper Interconnections of System-in-Packaging Structure using Finite Element Method," ICEPT-HDP2008, 28-31 July, Shanghai, China.
	C. Y. Chou, T. Y. Hung, M. C. Yew, W. K. Yang, D. C. Hu, M. C. Tsai, C. S. Huang, and K. N. Chiang, "Investigation of Stress-buffer-enhanced Package Subjected to Board-level Drop Test," EuroSimE2008, 20-23 April, Freiburg im Breisgau, Germany.
	S. Y. Chiang, C. Y. Chou, M. C. Yew, and K. N. Chiang, "Reliability Analysis of Copper Interconnection in System-in-package Structure," International Conference on Electronics Materials and Packaging (EMAP2007), November 19-22, 2007, Daejeon, Korea.
	C. J. Huang, C. Y. Chou, C. J Wu, and K. N. Chiang, "Investigation of the mechanical properties of nano-scale metallic crystal structural with point defects," European Nano System 2007 (ENS'07), December 3-4, 2007, Paris, France
	M. C. Yew, C. Y. Chou, and K. N. Chiang, "Reliability assessment for solders with a stress buffer layer using ball shear strength test and board-level finite element analysis." Microelectronics Reliability, Vol. 47, pp. 1658-1662, 2007.
	C. Y. Chou, C. J. Wu, H. P. Wei, M. C. Yew, C. C. Chiu, and K. N. Chiang, "Thermal management on hot spot elimination / junction temperature reduction for high power density system in package structure," InterPACK 2007, July 8-12, 2007, Vancouver, BC, Canada.
	Chan-Yen Chou, Chung-Jung Wu, Hsiu-Ping Wei, Ming-Chih Yew, Chien-Chia Chiu and Kuo-Ning Chiang, "Thermal Management on Hot Spot Elimination / Junction Temperature Reduction for High Power Density RF Multi-chip Module," Thermal Stress 2007, June 4-7, 2007, Taipei, Taiwan.
	C. N. Han, C. Y. Chou, and K. N. Chiang, "Investigation of Mechanical Strength of The Nanoshell of Bacteriophage Phi-29," NSTI Nanotech2007, May20-24, 2007, Santa Clara, USA.
	C. N. Han, C. Y. Chou, and K. N. Chiang, "Investigation of dsDNA Molecule Mechanical Behavior Using Atomistic Continuum Mechanics Method," NSTI Nanotech2007, May20-24, 2007, Santa Clara, USA.
	C. J. Wu, C. Y. Chou, C. N. Han, and K. N. Chiang, "Simulation and Validation of CNT Mechanical Properties – The Future Interconnection Material.", Electronic Components and Technology Conference (ECTC 2007), May 30 - Jun. 1, Reno, USA.
	Chun-Te Lin, Chan-Yen Chou, and Kuo Ning Chiang, "Estimation and validation of mechanical properties of single crystal silicon by atomic-level numerical model," Accepted in International Conference on Experimental Mechanics (ICEM13), Alexandroupolis, Greece, July1-6, 2007.
	K. N. Chiang, C. Y. Chou, and C. J. Wu, and C. A. Yuan, "Prediction of The Bulk Elastic Constant of Metals Using Atomic-Level Single-Lattice Analytical Method" Appl. Phys. Lett. 88, 171904, 2006
	Chun-Te Lin, Chan-Yen Chou, Chao-Jen Huang, and Kuo-Ning Chiang, "Validation of mechanical properties of the nanoscale single crystal IV-A group material by Atomistic-Continuum Mechanics Model," The 30th Conference of Theoretical and Applied Mechanics, 2006 12/15~12/16, Taiwan.
	M. C. Yew, C. Y. Chou, C. S. Huang, W. K. Yang, K. N. Chiang, "The Solder on Rubber (SOR) Interconnection Design and Its Reliability Assessment Based on Shear Strength Test and Finite Element Analysis," Journal of Microelectronics Reliability, Vol. 46, 2006, pp. 1874-1879
	Cadmus Yuan, Chan-Yen Chou, Cheng-Nan Han, Ming-Chih Yew and Kou-Ning Chiang,"12" to 8" wafer transformationn technique using novvel glass WLCSP structure," Proceedings of the IMAPS-Taiwan 2006 Technical Symposium, June 28 - July 1, 2006, Taipei World Trade Center, Taipei, Taiwan.
	C. Yuan, G. Q. Zhang, C. S. Huang, C. H. Yu, C. C. Yang, W. K. Yang, M. C. Yew, C. Y. Chou and K. N. Chiang, "Design, Experiment and Analysis of the Solder on Rubber (SOR) structure of WLCSP," Proceedings of the 7th International conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSIME2006, Como (Milano), Italy, April 23 - 26, 2006, pp. 619-625.
	Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Chan-Yen Chou and Kuo-Ning Chiang , "Reliability Impact of Highly Temperature-Dependent Underfill Material to the Lead-Free Flip Chip Package," EuroSimE2006 international Conference, 2006,in Como (Milano), Italy.
	Chung-Jung Wu, Chan-Yen Chou, Cheng-Nan Han, Kuo-Ning Chiang, “Investigation of Carbon Nanotube Mechanical Properties Using The Atomistic-Continuum Mechanics Method.”, NSTI Nanotech 2006, Boston, Massachusetts ( USA), 2006.
	C. N. Han, C. Y. Chou, C. J. Wu and K. N. Chiang, “Investigation of ssDNA Backbone Molecule Mechanical Behavior Using Atomistic-Continuum Mechanics Method”, NSTI 2006 Nanotechnology Conference, May 7-11, 2006, Boston, Massachusetts, U.S.A.
	C. Yuan, C. N. Han, C. Y. Chou, M. C. Yew and K. N. Chiang, "Simulation of unzipping dsDNA mechanical response using Clustered Atomistic-Continuum Method." ICCES'05 International Conference, Dec. 1-6, 2005, in Chennai, India.
	Chan-Yen Chou, Cadmus Yuan, Chung-Jung Wu and Kuo -Ning Chiang, "Numerical Simulation of the Mechanical Properties of Nanoscale Metal Clusters Using the Atomistic-Continuum Mechanics Method.", European Nano System 2005, 14-16 December 2005, Paris, France.
	K. N. Chiang , C.A. Yuan, C. N. Han, C. Y. Chou and Yujia Cui,"Mechanical Characteristic of ssDNA/dsDNA Molecule Under External Loading", Appl. Phy. Lett., 88, 023902, 2006, also published in the January 23, 2006 issue of Virtual Journal of Nanoscale Science & Technology.
	C. H. Chang, C. Y. Chou, C. N. Han, C. T. Peng, K. N. Chiang, “ Local-Strain Effect of the SiNx/Si Stacking and Nano-Scale Triple Gate Si/SiGe MOS Transistor”, published at Microelectronics, MEMS, and Nanotechnology 2005 (SPIE), Brisbane, Australia, Dec. 11–14 2005.
	C. Y. Chou, C. A. Yuan, and K. N. Chiang, "Investigation of Nano-scaled Material Behavior Using Atomistic-Continuum Mechanics Method." The 22nd National Conference on Mechanical Engineering, CSME, Nov. 25-26, C11-006, 2005.
	C. A. Yuan , C. N. Han, M. C. Yew, C. Y. Chou and K. N. Chiang, “Design, Analysis and Development of Novel Three-Dimensional Stacking WLCSP,” IEEE Transaction of Advanced Packaging, Vol 28, No. 3, pp. 387-396, Aug. 2005.
	C. H. Chang, C. Y. Chou, C. T. Peng, C. N. Han, and K. N. Chiang, “Investigation of Local-Strain Effect of the Nano-Scale Triple Gate Si/SiGe and SiNx/Si Stacking MOS Transistor.” NSTI Nanotechnology Conference, May 8-12, 2005, Anaheim, California, U.S.A.

參與計畫:

	2009.04~now 台達電計畫合作案,以破壞力學理論及模擬分析法預估電力模組的接點可靠度研究
	2007.08~2008.07 育霈科技計畫合作案, The Drop Test Analysis of Novel Slide-able Cu Trace Wafer Level Chip Scale Package
	2006.08~2007.07 育霈科技計畫合作案, Optimal Design and Reliability Analysis for Heat Dissipation Structure of Wafer Level Multi-chip Module
	2005.04~2006.07 育霈科技計畫合作案, The Reliability Analysis of Novel Slide-able Cu Trace Wafer Level Chip Scale Package
	2005.01~2006.02 台積電研究計畫－Low-k/Copper Interface
	2004.12~2009.06 工研院專利搜尋
	2004.02~2007.07 行政院國家科學委員會奈米國家型科技計畫利用單分子操控術進行DNA奈米劑量之創新研究
	2004.04~2004.05 裕沛科技研究計畫－WLCSP
	2003.08~2004.12 工研院自主性前瞻計畫－5X/16X資料庫設計

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周宗燐

博士班2010年畢

E-mail: tsunglin0502@webmail.pme.nthu.edu.tw

Homepage:

畢業論文：

高亮度發光二極體製程模擬與可靠度提昇之研究

相關著作:

Journal Paper

Tsung-Lin Chou, Chen-Hung Chu, Hsin-Nan Chiang, and Kuo-Ning Chiang, “Investigation of Thermal Hysteresis Phenomenon and Package Effect of MEMS Pressure Sensor,” Electronic Monthly, Volume 168, pp. 150-167, July 2009. (in Chinese)

Tsung-Lin Chou, Chen-Hung Chu, Chun-Te Lin and Kuo-Ning Chiang, “Sensitivity analysis of packaging effect of silicon-based piezoresistive pressure sensor,” Sensors & Actuators: A. Physical, Volume 152, Issue 1, pp. 29-38, 21 May 2009.

C.C. Chiu, C.C. Lee, T. L. Chou, C. C. Hsia, K.N. Chiang, “Analysis of Cu/Low-k Structure under Back End of Line Process,” Microelectronic Engineering, Volume 85 , Issue 10, October 2008.

Conference Paper

Tsung-Lin Chou, Chien-Fu Huang, Cheng-Nan Han, Shin-Yueh Yang, and Kuo-Ning Chiang, “Fabrication Process Simulation and Reliability Improvement of High- brightness LEDs,” 20^th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF2009), October 5-9, 2009, Arcachon, France (All accepted contributions to the conference have been published as a special issue of Microelectronics Reliability.)

W. H. Chi, T. L. Chou, C. N. Han, S. Y. Yang, and K. N. Chiang, "Analysis of Thermal Performance for High Power Light Emitting Diodes Lighting Module", International Conference on Electronics Packaging (ICEP 2009), April 14-16, 2009, Kyoto, Japan.

Wei-Hao Chi, Tsung-Lin Chou, Cheng-Nan Han, and Kuo-Ning Chiang, "Analysis of Thermal Performance of High Power Light Emitting Diodes Package," 10th Electronics Packaging Technology Conference, December, 2008, Singapore.

T. L. Chou, Z. H. Shih, H. F. Hong, C. N. Han, K. N. Chiang‚ “Investigation of Thermal Performance of High-Concentration Photovoltaic Solar Cell System,” 23rd European Photovoltaic Solar Energy Conference and Exhibition (EU PVSEC), Sep. 1-5, 2008, Valencia, Spain.

C.C. Lee, T.L. Chou, C.C. Chiu, C.C. Hsia, K.N. Chiang, “Cracking energy estimation of ultra low-k package using novel prediction approach combined with global-local modeling technique,” Materials for Advanced Metallization Conference 2008 (MAM2008), March 2-5, 2008, Dresden, Germany. (All accepted contributions to the conference will be published as a special issue of Microelectronic Engineering.)

C.C. Chiu, C.C. Lee, T. L. Chou, C. C. Hsia, K.N. Chiang, “Analysis of Cu/Low-k Structure under Back End of Line Process,” Materials for Advanced Metallization Conference 2008 (MAM2008), March 2-5, 2008, Dresden, Germany. (All accepted contributions to the conference will be published as a special issue of Microelectronic Engineering.)

T. L. Chou, Z. H. Shih, H. F. Hong, C. N. Han, K. N. Chiang‚ “Investigation of Thermal Performance of High-Concentration Photovoltaic Solar Cell Package,” International Conference on Electronics Materials and Packaging (EMAP2007), November 19-22, 2007, Daejeon, Korea. (Best Student Paper Award)

H. N. Chiang, T. L. Chou, C. T. Lin, K. N. Chiang‚ “Investigation of the Hysteresis Phenomenon of A Silicon-based Piezoresistive Pressure Sensor,” International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT2007), October 01-03, 2007, Taipei, Taiwan.

C. H. Chu, T. L. Chou, C. T. Lin, K. N. Chiang, “Investigation of Packaging Effect of Silicon-Based Piezoresistive Pressure Sensor,” Intl. Mechanical Engineering Congress and Exposition (ASME2006), November 05-10, 2006, Chicago, USA.

參與計畫:

晶元光電計畫合作案：LED 晶片極限強度測試與最佳化設計Determination Maximum Strength and Optimization of LED Chip Structure (2009,03~迄今)
行政院原子能委員會核能研究所委託研究計畫：太陽電池接收器結構與可靠度封裝技術之模擬及分析 Reliability Analysis of Photovoltaic Module Structure (2009,02~迄今)
晶元光電計畫合作案：LED 晶片多層膜界層破裂分析與最佳化設計 Crack Analysis and optimization of Multilayer Structure of LED Chip (2008,03~2009,02)
行政院原子能委員會核能研究所委託研究計畫：高倍率聚光型太陽電池封裝技術開發 Analysis and Design of High-Concentration Photovoltaic Solar Cell Package (2008,01~2008,12)
晶元光電計畫合作案：LED 晶片之可靠度與最佳化設計 Reliability Characteristics Analysis and Optimal Design of LED chip (2007,03~2008,3)
行政院原子能委員會核能研究所委託研究計畫：聚光型太陽電池封裝技術研發 Analysis and Design of High-Concentration Photovoltaic Solar Cell Package (2007,01~2007,12)
榮總台灣聯合大學合作研究計畫：超低壓力之矽材微壓阻式壓力感測器之設計與分析 The Design and Analysis of Ultra-Low Silicon-Based Piezoresistive Pressure Sensor (2006,01~2006,12)
工研院專利搜尋 (2006.01~迄今)

吳仲融

博士班2010年畢

E-mail: d9533807@oz.nthu.edu.tw

Homepage: More about me! 更多關於我 !

畢業論文：

界面強度模擬於三維晶片堆疊電子封裝與四點彎折界面強度測試之應用

相關著作 Publication:

期刊論文 Journal Papers:

	C. J. Wu, M. C. Hsieh, C. C. Chiu, M. C. Yew, and K. N. Chiang, "Interfacial delamination investigation between copper bumps in 3D chip stacking package by using the modified virtual crack closure technique," Microelectronic Engineering, in press.
	C. J. Wu, M. C. Hsieh, and K. N. Chiang, "Strength evaluation of silicon die for 3D chip stacking packages using ABF as dielectric and barrier layer in through-silicon via," Microelectronic Engineering, vol. 87, pp. 505-509, 2010.
	C. J. Wu, C. Y. Chou, C. N. Han, and K. N. Chiang, "Estimation and Validation of Elastic Modulus of Carbon Nanotubes Using Nano-Scale Tensile and Vibrational Analysis," Computer Modeling in Engineering and Science, Vol. 41, No. 1, pp. 49-68, 2009.
	M. C. Yew, C. C. A. Yuan, C. J. Wu, D. C. Hu, W. K. Yang, and Kuo-Ning Chiang, “Investigation of the Trace Line Failure Mechanism and Design of Flexible Wafer Level Packaging,” IEEE Transactions on Advanced Packaging, Volume, 32, No. 2, pp. 390-398, 2009.
	K. N. Chiang, C. Y. Chou, C. J. Wu, C. J. Huang, and M. C. Yew, "Analytical solution for estimation of temperature-dependent material properties of metals using modified Morse potential," Computer Modeling in Engineering and Science, Vol. 37, No. 1, pp. 85-96, 2008.
	C. C. Chiu, C. J. Wu, C. T. Peng, K. N. Chiang, T. Ku, and K. Cheng, "Failure life prediction and factorial design of lead-free flip chip package," Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers, Vol.30, No. 3, pp. 481-490, 2007.
	K. N. Chiang, C. Y. Chou, and C. J. Wu, and C. A. Yuan, "Prediction of The Bulk Elastic Constant of Metals Using Atomic-Level Single-Lattice Analytical Method" Appl. Phys. Lett. 88, 171904, 2006.

會議論文 Conference Papers:

	C. J. Wu, M. C. Hsieh, and K. N. Chiang, "Delamination Investigation of Copper Bumps in 3D Chip Stacking Packages Using the Modified Virtual Crack Closure Technique," International Conference on Electronics Packaging, ICEP 2010, Sapporo, Japan, May 12-14, 2010.
	C. J. Wu, M. C. Hsieh, C. C. Chiu, M. C. Yew, and K. N. Chiang, "Interfacial Delamination Investigation between Copper Bumps in 3D Chip Stacking Package by Using the Modified Virtual Crack Closure Technique," Materials for Advanced Metallization Conference, MAM 2010, Mechelen, Belgium, Mar. 7-10, 2010.
	C. J. Wu, M. C. Hsieh, and K. N. Chiang, "Die-Cracking Evaluation of Silicon Chip Covered with Polymer Film for 3D Chip Stacking Packages," International Conference on Electronics Packaging, ICEP 2009, Kyoto, Japan, Apr. 14-16, 2009.
	C. J. Wu, M. C. Hsieh, and K. N. Chiang, "Strength Evaluation of Silicon Die for 3D Chip Stacking Packages Using ABF as Dielectric and Barrier Layer in Through-Silicon Via," Materials for Advanced Metallization Conference, MAM 2009, Grenoble, France, Mar. 8-11, 2009.
	C. J. Wu, C. Y. Chou, C. N. Han, and K. N. Chiang, "Simulation and Validation of SWCNT Mechanical Properties," Taiwan ANSYS/Fluent Conference, 2008, Taipei, Taiwan.
	H. P. Wei, M. C. Yew, C. J. Wu, and K. N. Chiang, "Reliability and Thermal Assessment of Stacked Chip-on-Metal Panel Based Package (PBPTM) with Fan-Out Capability," 2nd Electronics System-Integration Technology Conference, ESTC 2008, London, England, Sep. 01-04, 2009,.
	Ming-Chih Yew, Chung-Jung Wu and Kuo-Ning Chiang, "Trace Line Failure Analysis and Characterization of the Panel Base Package (PBPTM) Technology with Fan-Out Capability," Proceedings of the 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITherm 2008, pp. 862-869, Florida, USA, May 28 -31, 2008.
	C. J. Wu, C. Y. Chou, C. N. Han, and K. N. Chiang, "Estimation and Validation of Elastic Modulus of Carbon Nanotubes Using Nano-Scale Tensile and Vibrational Analysis," International Conference on Computational & Experimental Engineering and Sciences 2008, ICCES'08, Honolulu, Hawaii, USA, Mar. 16-21, 2008.
	C. J. Huang, C. Y. Chou, C. J. Wu, and K. N. Chiang, "Investigation of the mechanical properties of nano-scale metallic crystal structural with point defects," European Nano System 2007 (ENS'07), Dec. 3-4, 2007, Paris, France
	C. Y. Chou, C. J. Wu, H. P. Wei, M. C. Yew, C. C. Chiu, and K. N. Chiang, "Thermal management on hot spot elimination / junction temperature reduction for high power density system in package structure," InterPACK 2007, Jul. 8-12, 2007, Vancouver, BC, Canada.
	Chan-Yen Chou, Chung-Jung Wu, Hsiu-Ping Wei, Ming-Chih Yew, Chien-Chia Chiu and Kuo-Ning Chiang," Thermal Management on Hot Spot Elimination / Junction Temperature Reduction for High Power Density RF Multi-chip Module," Thermal Stress 2007, Jun. 4-7, 2007, Taipei, Taiwan.
	C. J. Wu, C. Y. Chou, C. N. Han, and K. N. Chiang, "Simulation and Validation of CNT Mechanical Properties – The Future Interconnection Material," Electronic Components and Technology Conference (ECTC 2007), May 30 - Jun. 1, Reno, USA.
	Chung-Jung Wu, Chan-Yen Chou, Cheng-Nan Han, Kuo-Ning Chiang, "Numerical Simulation of the Mechanical Properties of Carbon Nanotube Using the Atomistic-Continuum Mechanics," European Nano System 2006, Dec. 14-15, 2006, Paris, France.
	Chung-Jung Wu, Chan-Yen Chou, Cheng-Nan Han, Kuo-Ning Chiang, “Investigation of Carbon Nanotube Mechanical Properties Using The Atomistic-Continuum Mechanics Method,” NSTI Nanotech 2006, Boston, Massachusetts ( USA), 2006.
	Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Chan-Yen Chou and Kuo-Ning Chiang , "Reliability Impact of Highly Temperature-Dependent Underfill Material to the Lead-Free Flip Chip Package," EuroSimE2006 international Conference, 2006,in Como (Milano), Italy.
	Chan-Yen Chou, Cadmus Yuan, Chung-Jung Wu and Kuo -Ning Chiang, "Numerical Simulation of the Mechanical Properties of Nanoscale Metal Clusters Using the Atomistic-Continuum Mechanics Method," European Nano System 2005, 14-16 December 2005, Paris, France.
	Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Kuo-Ning Chiang, Terry Ku and Kenny Cheng "Reliability Assessment of Lead-Free Flip Chip Package Using Factorial Design Methodology," Taiwan ANSYS User Conference, 2005
	Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Kuo-Ning Chiang, Terry Ku and Kenny Cheng "Reliability Analysis and Factorial Design of Lead-Free Flip Chip Package Using THE Finite Element Method," Proceedings of IPACK2005, International Electric Packaging Technical Conference and Exhibition, San Francisco, California, USA, 2005

參與計畫 Project：

	工研院暨國立清華大學學界分包研究計畫 – 製程殘餘應力分析模型的開發 (2009.08~迄今) ITRI Project – Stress/Strain Analysis of MEMS Multi-Layer Structure Using Process Modeling Technology (2009.08~Now)
	工業技術研究院委託學術機構研究計畫 – 3DIC-SiP 介面可靠度分析與驗證 (2009.01~2009.12) ITRI Project – Validation and Analysis of the Interfacial Reliability of 3DIC-SiP (2009.01~2009.12)
	中華民國台灣薄膜電晶體液晶顯示器產業協會(工業技術研究院) – 複合凸塊專利搜尋 (2006.07~2009.11) Taiwan TFT LCD Association, TTLA (ITRI) – "Composite Bump" Patents Search (2006.07~2009.11)
	工業技術研究院委託學術機構研究計畫 – SiP疊孔結構介面應變能釋放率之驗證與用 (2008.01~2008.12) ITRI Project – Validation and Application of Strain Energy Release Rate of the Interconnect Via in System-in-Packaging (2008.01~2008.12)
	工業技術研究院委託學術機構研究計畫 – SiP疊孔Interconnects介面破裂模型 (2007.01~2007.12) ITRI Project – Crack Model of the Interconnect Via in System-in-Packaging (2007.01~2007.12)
	育霈科技計畫合作案 – The Reliability Analysis of Novel Slide-able Cu Trace Wafer Level Chip Scale Package (2006.07~2007.03)
	行政院國家科學委員會奈米國家型科技計畫 – 利用單分子操控術進行DNA奈米劑量之創新研究(2005.09~2007.07)
	威盛電子 – 覆晶封裝結構可靠度之參數化有限元素分析與設計 (2004.09~2005.07)

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張香鈜

E-mail: mikechang@itri.org.tw

畢業論文：

熱與應力耦合效應對導線內電子遷移的影響研究

相關著作 Publication:

期刊論文Journal Papers

C. C. Chiu, H. H. Chang, C. C. Lee, C. C. Hsia, and K. N. Chiang, "Reliability of interfacial adhesion in a multi-level copper/low-k interconnect structure," Microelectronics Reliability, vol. 47, pp. 1506-1511, Sep-Nov 2007.

會議論文Conference Papers

	H. H. Chang, J. H. Huang, C. W. Chiang, Z. C. Hsiao, H. C. Fu, C. H. Chien, Y. H. Chen, W. C. Lo, and K. N. Chiang, “Process Integration and Reliability Test for 3D Chip Stacking with Thin Wafer Handling Technology,” in Electronic Components and Technology Conference, May 31-Jun. 3, Florida, US, 2011.
	W. L. Tsai, H. H. Chang, C. H. Chien, J. H. Lau, H. C. Fu, C. W. Chiang, T. Y. Kuo, Y. H. Chen, R. Lo and M. J. Kao, “How to Select Adhesive Materials for Temporary Bonding and De-Bonding of 200mm and 300mm Thin-Wafer Handling for 3D IC Integration?,” in Electronic Components and Technology Conference, May 31-Jun. 3, Florida, US, 2011.
	Sheng-Ho Huang*, Chun-Hsing Lee, Hung-Lien Hu, Mu-Tao Chu, Jen-Hao Yeh, Yuan-Chin Chen, Yu-Ming Huang, Chao-Kai Hsu, Hsiang-Hung Chang and Huan-Chun Fu, “A Low Cost Rigid-Flex Opto-electrical Link for Mobile Devices,” in International Microsystems, Packaging, Assembly and Circuits Technology Conference, Oct. 20-22, Taipei, Taiwan, 2010.
	H. H. Chang, J. H. Huang, C. W. Chiang, Z. C. Hsiao, H. C. Fu, Y. H. Chen and K. N. Chiang, “Process Integration for 3D Chip Stacking with Thin Wafer Handling Technology,” in Materials for Advanced Metallization Conference, Mar. 7-10, Mechelen, Belgium, 2010.
	H. H. Chang, Y. C. Shih, Z. C. Hsiao, C. W. Chiang, Y. H. Chen, and K. N. Chiang, “3D Stacked Chip Technology Using Bottom-up Electroplated TSVs,” in Electronic Components and Technology Conference, May 26-29, San Diego, CA, US, 2009.
	T. Y. Kuo, Y. C. Shih, Y. C. Lee, H. H. Chang, Z. C. Hsiao, C. W. Chiang, S. M. Li, Y. J. Hwang, C. T. Ko, Y. H. Chen, “Flexible and Ultra-Thin Embedded Chip Package,” in Electronic Components and Technology Conference, May 26-29, San Diego, CA, US, 2009
	H. H. Chang, Y. C. Shih, C. K. Hsu, Z. C. Hsiao, C. W. Chiang, Y. H. Chen, and K. N. Chiang, “TSV Process Using Bottom-up Cu Electroplating and its Reliability Test,” in Electronics System-Integration Technology Conference, September 1-4, Greenwich, UK, 2008.
	S. G. Lee, C. H. Lee, C. C. Lu, F. Y. Cheng, K. Y. Shen, S. H. Huang, L. C. Shen, S. M. Chang, H. H. Chang, H. C. Fu, P. Tien, M. T. Chu, and Y. J. Chan, “Recent Trend of Optical Circuit Board in Taiwan,” in Polymers and Adhesives in Microelectronics and Photonics, January 16-18, Odaiba, Tokyo, Japan, 2007.
	W. C. Lo, S. M. Chang, Y. H. Chen, J. D. Ko, T. Y. Kuo, H. H. Chang, Y. C. Shih, “3D Chip-to-Chip Stacking with Through Silicon Interconnects,” in International Symposium on VLSI Technology, Systems and Applications, April 23-25, Hsinchu, Taiwan, 2007.
	H. H. Chang, W. C. Lo, L. C. Shen, H. C. Fu, Y. C. Lee, and S. M. Chang, “Interconnection of Flexible Electronic-Optical Circuit Board Module,” in International Microsystems, Packaging, Assembly and Circuits Technology Conference, October 18-20, Taipei, Taiwan, 2006
	L. C. Shen, W. C. Lo, H. H. Chang, H. C. Fu, Y. C. Lee, S. M. Chang, Y. C. Chen, and W. Y. Chen, “Flexible Electronic-Optical Local Bus Modules to the Board-to-Board, Board-to-Chip, and Chip-to-Chip Optical Interconnection,” in Electronic Components and Technology Conference, May 31- June 3, Lake Buena Vista, Florida, US, 2005.
	L. C. Shen, W. C. Lo, H. H. Chang, H. C. Fu, Y. C. Lee, Y. C. Chen, S. M. Chang, W. Y. Chen, and M. C. Chou, “Characterization of Organic Multi-mode Optical Waveguides for the Electro-Optical Printed Circuit Board (EOPCB),” in Electronics Packaging Technology Conference, December 8-10, Singapore, 2004.
	W. C. Lo, L. C. Shen, H. H. Chang, H. C. Fu, Y. C. Chen, S. M. Chang, Y. C. Lee, W. Y. Chen, M. C. Chou, “Polymeric Waveguides on Rigid and Flexible PCB,” in Electronic Components and Technology Conference, June 1-4, Las Vegas, US, 2004.

Patents

	Taiwan Patent No. I324058
	Taiwan Patent No. I332790
	China Patent No. ZL200710112678.9
	US Patent No. 7,663,231
	US Patent Application No. 12/155,715
	US Patent Application No. 12/500,780
	Taiwan Patent Application No. 96125246
	Taiwan Patent Application No. 97120592
	Taiwan Patent Application No. 97129949
	Taiwan Patent Application No. 98140290
	China Patent Application No. 200810213229.8
	China Patent Application No. 201010606570.7
	Taiwan Patent Application No. 99140809
	US Patent Application No. 13/037,372

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黃昭荏

博士班2012年畢

E-mail: d9633834@oz.nthu.edu.tw

相關著作:

Journal Papers

	T. Y. Hung, C. J. Huang, C. C. Lee, C. C. Wang, K. C. Lu, and K. N. Chiang, " Investigation of Solder Crack Behavior and Fatigue Life of the Power Module on Different Thermal Cycling Period," has been accepted for publication in Microelectronic Engineering
	K. N. Chiang, C. Y. Chou, C. J. Wu, C. J. Huang, and M. C. Yew, "Analytical Solution for Estimation of Temperature-Dependent Material Properties of Metals Using Modified Morse Potential," Cmes-Computer Modeling in Engineering & Sciences, vol. 37, pp. 85-96, Nov 2008.
	C. C. Chiu, C. J. Huang, S. Y. Yang, C. C. Lee, and K. N. Chiang, "Investigation of the delamination mechanism of the thin film dielectric structure in flip chip packages," Microelectronic Engineering, vol. 87, pp. 496-500, Mar 2010.
	C. Y. Chou, T. Y. Hung, C. J. Huang, and K. N. Chiang, "Development of Empirical Equations for Metal Trace Failure Prediction of Wafer Level Package Under Board Level Drop Test," Ieee Transactions on Advanced Packaging, vol. 33, pp. 681-689, Aug 2010.
	C. J. Huang, C. J. Wu, H. A. Teng, and K. N. Chiang , "A Robust Nano-Mechanics Approach for Tensile and Modal Analysis Using Atomistic-Continuum Mechanics Method" Computational Materials Science, vol.50, pp.2245-2248, 2011.
	T. Y. Hung, S. Y. Chiang, C. J. Huang, C. C. Lee, and K. N. Chiang, "Thermal-mechanical behavior of the bonding wire for a power module subjected to the power cycling test," Microelectronics Reliability, in press.

Conference Papers

	T. Y. Hung, C. J. Huang, C. C. Lee, C. C. Wang, K. C. Lu, and K. N. Chiang, "Thermal Cycling Period Effect of Fatigue Life of the Power Module," Materials for Advanced Metallization Conference, MAM 2012, Grenoble, France, Mar. 11-14, 2012.
	C. J. Huang, T. Y. Hung, K. N. Chiang, "Analysis of the Mechanical Properties of Si/SiGe Heterostructure using Atomistic-continuum Mechanics with Constraint Equations,"APMC-10, ICONN 2012 & ACMM-22, Perth, WA Australia Feb. 5-9, 2012.
	T. Y. Hung, S. Y. Chiang, C. J. Huang, C. C. Wang, K. C. Lu, and K. N. Chiang, "Dwell Time Effect and Thermal Fatigue Life Assessment of Power Module," 13th International Conference on Electronics Materials and Packaging, 3 pp. 2011, Kyoto, Japan
	T. Y. Hung, S. Y. Chiang, C. J. Huang, C. C. Lee, K. N. Chiang, "Thermal-mechanical behavior of the bonding wire for a power module subjected to the power cycling test," 22nd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), October 3-7, 2011, Bordeaux, France.
	C. J. Huang, C.J. Wu, H.A. Teng, and K.N. Chiang, "Research on Multi-Scale Structural Analysis using the Atomistic-Continuum Equivalent Mechanics," CSWNST-8, Hong Kong, Dec. 19-22, 2010.
	C. J. Huang, C. J. Wu, H. A. Teng, K. N. Chiang, “Carbon nanotubes structural mechanics using the atomistic-continuum mechanics and equivalent methods” ACCM-7, Taipei, Taiwan, Nov. 15-18, 2010.
	C. J. Huang, C. J. Wu, H. A. Teng, and K. N. Chiang "A Robust Nano-Mechanics Approach for Tensile and Modal Analysis Using Atomistic-Continuum Mechanics Method," ICONN 2010, Sydney, Australia, Feb 22-26, 2010.
	M. Sano, C. Y. Chou, T. Y. Hung, S. Y. Yang, C. J. Huang, and K. N. Chiang, "Reliability and parametric study on chip scale package under board-level drop test," 4th IMPACT, Taipei, Taiwan, Oct. 21-23, 2009.
	C. Y. Chou, C. J. Huang, M. Sano, and K. N. Chiang, "Metal trace impact life prediction model for stress buffer enhanced package," 17th European Microelectronics and Packaging Conference & Exhibition (EMPC2009), Rimini, Italy, June 15-18, 2009.
	C. J. Huang, C. Y. Chou, K. N. Chiang, “Dynamic study and structure enhancement of small outline dual-in-line memory module”, International Conference on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE2009), Delft, Netherlands, April 27-29, 2009.
	C. C. Chiu, C. J. Huang, S. Y. Yang, C. C. Lee, and K. N. Chiang, "Investigation of the delamination mechanism of the thin film dielectric structure in flip chip packages" Materials for Advanced Metallization Conference (MAM 2009), Grenoble, France, Mar. 8-11, 2009.
	C. J. Huang, C. Y. Chou, C. J Wu, and K. N. Chiang, "Investigation of the mechanical properties of nano-scale metallic crystal structural with point defects," European Nano System 2007 (ENS'07), Paris, France, Dec. 3-4, 2007.
	H. P. Wei, M. C. Yew, C. J. Huang, and K. N. Chiang, "Failure mode and thermal performance analysis of stacked panel level package (PLP)," InterPACK 2007, Vancouver, BC, Canada, July 8-12, 2007.
	C. T. Lin, C. Y. Chou, C. J. Huang, and K. N. Chiang, "Validation of mechanical properties of the nanoscale single crystal IV-A group material by Atomistic-Continuum Mechanics Model," The 30th Conference of Theoretical and Applied Mechanics, Taiwan, Dec. 15-16, 2006.

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楊炘岳

博士班2012年畢

E-mail: d9633805@oz.nthu.edu.tw

相關著作:

Journal Papers

	T. L. Chou, S. Y. Yang, and K. N. Chiang, “Overview and applicability of residual stress estimation of film-substrate structure,” Thin Solid Films,” Volume 519, Volume 519, Issue 22, pp. 7883-7894, 2011.
	T. L. Chou, S. Y. Yang, C. J. Wu, C. N. Han, and K. N. Chiang, “Measurement and simulation of interfacial adhesion strength between SiO2 thin film and III-V material,” Microelectronics Reliability, Volume 51, Issue 9-11, pp. 1757-1761, 2011.
	Y. F. Su, S. Y. Yang, T. Y. Hung, C. C. Lee, and K. N. Chiang, "Light degradation test and design of thermal performance for high-power light-emitting diodes," Microelectronics Reliability, in press
	W. H. Chi, T. L. Chou, C. N. Han, S. Y. Yang, and K. N. Chiang, "Analysis of Thermal and Luminous Performance of MR-16 LED Lighting Module," Ieee Transactions on Components and Packaging Technologies, vol. 33, pp. 713-721, Dec 2010.
	C. C. Chiu, C. J. Huang, S. Y. Yang, C. C. Lee, and K. N. Chiang, "Investigation of the delamination mechanism of the thin film dielectric structure in flip chip packages," Microelectronic Engineering, vol. 87, pp. 496-500, Mar 2010.
	C. Y. Chou, T. Y. Hung, S. Y. Yang, M. C. Yew, W. K. Yang, and K. N. Chiang, "Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact," Microelectronics Reliability, vol. 48, pp. 1149-1154, Aug-Sep 2008.
	T. L. Chou, C. F. Huang, C. N. Han, S. Y. Yang, and K. N. Chiang, "Fabrication process simulation and reliability improvement of high-brightness LEDs," Microelectronics Reliability, vol. 49, pp. 1244-1249, Sep-Nov 2009.
	T. L. Chou, S. Y. Yang, C. J. Wu, C. N. Han, and K. N. Chiang, “Measurement and simulation of interfacial adhesion strength between SiO2 thin film and III-V material,” Microelectronics Reliability, in press.

Conference Papers

	C. F. Huang, Y. F. Su, S. Y. Yang, C. L. Hsu, N. C. Chen, and K. N. Chiang, "Quantum Efficiency Investigation at high Current Density of Ultra-High-Brightness LEDs," ITHERM 2012, San Diego, California, USA, May 30 - June 1
	P. C. Chen, Y. F. Su, S. Y. Yang, and K. N. Chiang, "Determination of Silicon Die Initial Crack Using Acoustic Emission Technique," iMPACT 2011, Taipei, Taiwan, October 19-21, 2011
	T. L. Chou, S. Y. Yang, C. J. Wu, C. N. Han, and K. N. Chiang, “Measurement and simulation of interfacial adhesion strength between SiO2 thin film and III-V material,” ESREF 2011, Bordeaux, France, Oct. 3-7, 2011.
	S. Y. Chiang, S. Y. Yang, C. Y. Chou, M. C. Yew, and K. N. Chiang, "Reliability Analysis of Copper Interconnections of System-in-Packaging Structure using Finite Element Method," presented at the 2008 International Conference on Electronic Packaging Technology & High Density Packaging, Vols 1 and 2, 2008.
	M. Sano, C. Y. Chou, T. Y. Hung, S. Y. Yang, and K. N. Chiang, "Uncertainty and Reliability Analysis of Chip Scale Package Subjected to Board-level Drop Test," presented at the Eurosime 2009: Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2009.
	M. Sano, C. Y. Chou, T. Y. Hung, S. Y. Yang, C. J. Huang, K. N. Chiang, "Reliability and Parametric Study on Chip Scale Package Under Board-Level Drop Test," presented at the Impact: 2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference, 2009.
	S. Y. Yang, S. Y. Chiang, C. Y. Chou, M. C. Yew, K. N. Chiang, "Reliability Analysis of Copper Interconnections of System-in-Packaging," presented at the Impact: 2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference, 2009.
	S. Y. Yang, T. L. Chou, C. F. Huang, C. J. Wu, C. L. Hsu, and K. N. Chiang, "Strength determination of light-emitting diodes and chip structure design," in Microsystems Packaging Assembly and Circuits Technology Conference (IMPACT), 2010 5th International, 2010, pp. 1-4.
	S. Y. Yang, T. L. Chou, C. F. Huang, C. J. Wu, C. L. Hsu, and K. N. Chiang, "Determination of maximum strength and optimization of LED chip structure," in Electronic System-Integration Technology Conference (ESTC), 2010 3rd, 2010, pp. 1-5.
	Y. F. Su, S. Y. Yang, W. H. Chi, and K. N. Chiang, "Light degradation prediction of high-power light-emitting diode lighting modules," in Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE), 2010 11th International Conference on, 2010, pp. 1-6.
	C. Y. Chou, T. Y. Hong, M. Sano, S. Y. Yang, and K. N. Chiang, "Investigation of Influences of PCB on Board-level Drop Test by Dynamic Simulation and Modal Analysis," presented at the Microsystems, Packaging, Assembly & Circuits Technology Conference, 2008. IMPACT 2008. 3rd International, 2008.
	H. A. Deng, S. Y. Yang, C. N. Han, T. L. Chou, and K. N. Chiang "Warpage Analysis of High Power InGaN Light Emitting Diodes after Laser Lift-off," EMAP 2009, Penang, Malaysia, Dec 1-3, 2009.
	W. H. Chi, T. L. Chou, C. N. Han, S. Y. Yang, and K. N. Chiang, "Analysis of Thermal Performance for High Power Light Emitting Diodes Lighting Module", International Conference on Electronics Packaging (ICEP 2009),Kyoto, Japan, April 14-16, 2009
	C. Y. Chou, T. Y. Hung, S. Y. Yang, M. C. Yew, W. K. Yang, and K. N. Chiang, "Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact," ESREF2008, 30 Sep. - 03 Oct., Maastricht, Netherland.
	P. C. Chen, S. Y. Yang, K. N. Chiang "Determination and Verification of Silicon Die Strength Using Ball-Breaker Test," in InterPACK 2011, Jul 6-8, Portland, Oregon, USA, 2011

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黃建富

E-mail: Huangjanfu@hotmail.com

相關著作:

Journal Papers

	C. F. Huang, Y. F. Su, C. B. Lin, and K. N. Chiang,"Research on the degradation of AlGaInP Ultra High Brightness LEDs influenced by ohmic metal design," Microelectronic Engineering , Volume 120, 25 May 2014, Pages 182–187
	T. L. Chou, C. F. Huang, C. N. Han, S. Y. Yang, and K. N. Chiang, "Fabrication Process Simulation and Reliability Improvement of High- brightness LEDs," Microelectronics Reliability, Volume 49, Issue 9-11, pp. 1244-1249, 2009.
	C. F. Huang; Y. F. Su; C. B. Lin; K. N. Chiang, "Research on Efficiency Droop Mechanism and Improvement in AlGaInP Ultra-High-Brightness LEDs Using the Transient Measurement Method", Solid State Electronics, Accepted and to be published

Conference Papers

	C. F. Huang, Y. F. Su, C. B. Lin, and K. N. Chiang,"Research on the degradation of AlGaInP Ultra High Brightness LEDs influenced by ohmic metal design," Leuven, Belgium, March 10-13, 2013.
	C. F. Huang, Y. F. Su, S. Y. Yang, C. L. Hsu, N. C. Chen, and K. N. Chiang, "Quantum Efficiency Investigation at high Current Density of Ultra-High-Brightness LEDs," ITHERM 2012, San Diego, California, USA, May 30 - June 1
	S. Y. Yang, T. L. Chou, C. F. Huang, C. J. Wu, C. L. Hsu, and K. N. Chiang "Strength Determination of Light-emitting diodes and Chip Structure Design," IMPACT2010, Taipei, Taiwan, Oct 20-22, 2010.
	S. Y. Yang, T. L. Chou, C. F. Huang, C. J. Wu, C. L. Hsu, and K. N. Chiang "Determination of Maximum Strength and Optimization of LED Chip Structure," ESTC2010, Berlin, Germany, Sep 14-16, 2010.
	C. N. Han, T. L. Chou, C. F. Huang, and K. N. Chiang, "Sappire-removed induced the deformation of high power InGaN light emitting diodes," EuroSimE2008, Freiburg im Breisgau, Germany, April 20-23, 2008.

$描述: 描述: 描述: 描述: 描述: D:\www\csml\members\洪端佑.jpg$
　

洪端佑

E-mail: d9733804@oz.nthu.edu.tw

相關著作:

Journal Papers

	L. L. Liao, T. Y. Huang, C. K. Liu, W. Li, M. J. Dai, and K. N. Chiang, "Electro-thermal finite element analysis and verification of power module with aluminum wire", Microelectronic Engineering, Volume 120, 25 May 2014, Pages 114–120, MAM2013
	T. Y. Hung, L. L. Liao, C. C. Wang, W. H. Chi, and K. N. Chiang, "Life Prediction of High Cycle Fatigue in Aluminum Bonding Wires under Power Cycling Test", IEEE Transactions on device and materials reliability, Available online 05 November 2013, ISSN 1530-4388.
	C. J. Huang, T. Y. Hung, and K. N. Chiang, "Estimation of the Mechanical Property of CNT Ropes Using Atomistic-Continuum Mechanics and the Equivalent Methods," CMC-Computers, Materials, & Continua, Vol 36, No 2, pp. 99-133, Jul 2013
	T. Y. Hung, C. J. Huang, C. C. Lee, C. C. Wang, K. C. Lu, and K. N. Chiang, " Investigation of Solder Crack Behavior and Fatigue Life of the Power Module on Different Thermal Cycling Period," has been accepted for publication in Microelectronic Engineering
	Y. F. Su, S. Y. Yang, T. Y. Hung, C. C. Lee, and K. N. Chiang, "Light degradation test and design of thermal performance for high-power light-emitting diodes," Microelectronics Reliability, in press
	C. Y. Chou, T. Y. Hung, C. J. Huang, and K. N. Chiang, "Development of Empirical Equations for Metal Trace Failure Prediction of Wafer Level Package Under Board Level Drop Test," Ieee Transactions on Advanced Packaging, vol. 33, pp. 681-689, Aug 2010.
	C. Y. Chou, T. Y. Hung, S. Y. Yang, M. C. Yew, W. K. Yang, and K. N. Chiang, "Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact," Microelectronics Reliability, vol. 48, pp. 1149-1154, Aug-Sep 2008.
	T. Y. Hung, S. Y. Chiang, C. J. Huang, C. C. Lee, and K. N. Chiang, "Thermal-mechanical behavior of the bonding wire for a power module subjected to the power cycling test," Microelectronics Reliability, vol 51, issues 9-11, pp.1819-1823, 2011
	T. Y. Hung, L. L. Liao, C. C. Wang, W. H. Chi, and K. N. Chiang, "Life Prediction of High Cycle Fatigue in Aluminum Bonding Wires under Power Cycling Test", IEEE Transactions on device and materials reliability, Accepted and to be published

Conference Papers

	H. C. Huang, T. Y. Hung, S. Y. Lin, K. H. Liao, C. C. Wang, K. N. Chiang, "Reliability Assessment of the Temperature Profiles Effect on the Power Module", Published at The 29th National Conference on Theoretical and Applied Mechanics & The 1st International Conference on Mechanics, Nov 8-9, 2013, Hsinchu, Taiwan
	K.C. Lin, C.C. Tsai, Y.F. Su, T.Y. Hung, K.N. Chiang, "Analysis of LED Wire Bonding Process Using Arbitrary Lagrangian-Eulerian and Explicit Time Integration Methods", iMPACT2013, Taipei,Taiwan, Oct 23-25, 2013
	C.J. Huang, T.Y. Hung and K.N. Chiang, "The Mechanical Properties of Carbon Nanotubes Ropes Using Atomistic-Continuum Mechanics and the Equivalent Methods", ICCES 2013, May 24-28, Seattle, USA
	T. Y. Hung, C. C. Wang, and K. N. Chiang, "Bonding Wire Life Prediction Model of the Power Module under Power Cycling Test," EuroSimE 2013, Wroclaw, Poland, April 15-17, 2013.
	L. L. Liao, T. Y. Huang, C. K. Liu, W. Li, M. J. Dai, and K. N. Chiang, "Electro-thermal finite element analysis and verification of power module with aluminum wire", Materials for Advanced Metallization Conference, MAM 2013, Leuven, Belgium, Mar. 10-13, 2013
	C. T. Lai, T. Y. Hung, and K. N. Chiang, "Investigation on the Effect of Surface Roughness on the Fracture Strength of SCS", EuroSimE 2012, Lisbon, Portugal, April 16-18.
	H. H. Chang, T. Y. Hung, and K. N. Chiang, "Residual Stress Effect of Electromigration Behavior on Aluminum Strip," Materials for Advanced Metallization Conference, MAM 2012, Grenoble, France, Mar. 11-14, 2012.
	T. Y. Hung, C. J. Huang, C. C. Lee, C. C. Wang, K. C. Lu, and K. N. Chiang, "Thermal Cycling Period Effect of Fatigue Life of the Power Module," Materials for Advanced Metallization Conference, MAM 2012, Grenoble, France, Mar. 11-14, 2012.
	T. Y. Hung, S. Y. Chiang, C. J. Huang, C. C. Wang, K. C. Lu, and K. N. Chiang, "Dwell Time Effect and Thermal Fatigue Life Assessment of Power Module," 13th International Conference on Electronics Materials and Packaging, 3 pp. 2011, Kyoto, Japan
	T. Y. Hung, S. Y. Chiang, C. J. Huang, C. C. Lee, K. N. Chiang, "Thermal-mechanical behavior of the bonding wire for a power module subjected to the power cycling test," 22nd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), October 3-7, 2011, Bordeaux, France.
	C. Y. Chou, T. Y. Hung, M. C. Yew, W. K. Yang, D. C. Hu, M. C. Tsai, C. S. Huang and K. N. Chiang, "Investigation of stress-buffer-enhanced package subjected to board-level drop test," presented at the Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Micro-Systems, 2008. EuroSimE 2008. International Conference on, 2008.
	C. Y. Chou, T. Y. Hung, M. Sano, S. Y. Yang and K. N. Chiang, "Investigation of Influences of PCB on Board-level Drop Test by Dynamic Simulation and Modal Analysis," in Microsystems, Packaging, Assembly & Circuits Technology Conference, 2008. IMPACT 2008. 3rd International, 2008, pp. 185-188.
	T. Y. Hung, M. C. Yew, C. Y. Chou, K. N. Chiang, and Ieee, "A Study of Thermal Performance for Chip-in-Substrate Package on Package," presented at the 2009 European Microelectronics and Packaging Conference, 2009.
	M. Sano, C. Y. Chou, T. Y. Hung, S. Y. Yang, and K. N. Chiang, "Uncertainty and Reliability Analysis of Chip Scale Package Subjected to Board-level Drop Test," presented at the Eurosime 2009: Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2009.
	M. Sano, C. Y. Chou, T. Y. Hung, S. Y. Yang, C. J. Huang, K. N. Chiang, and Ieee, "Reliability and Parametric Study on Chip Scale Package Under Board-Level Drop Test," presented at the Impact: 2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference, 2009.
	T. Y. Hung, S. Y. Chiang, C. Y. Chou, C. C. Chiu, and K. N. Chiang, "Thermal design and transient analysis of insulated gate bipolar transistors of power module," presented at the Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2010 12th IEEE Intersociety Conference on, 2010.
	C. Y. Chou, T. Y. Hung, S. Y. Yang, M. C. Yew, W. K. Yang, and K. N. Chiang, "Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact," ESREF2008, 30 Sep. - 03 Oct., Maastricht, Netherland.
	S. Y. Syu, T. Y. Hung, C. J. Huang, H. J. Wang, H. L. Lee and K.N. Chiang, "Reliability Assessment of 3D Chip Stacking Package Using Metal Bonding and Through Silicon Via Technologies," ASME International Mechanical Engineering Congress & Exposition (IMECE), Vancouver, Canada, Nov. 12-18, 2010.
	S. Y. Chiang, T. Y. Hung, Ray Hsing and K. N. Chiang, "Temperature Dependent Current Crowding Analysis of Insulated Gate Bipolar Transistor," ICEP2010, Sapporo, Hokkaido, Japan, May 12-14, 2010.
	C. J. Wu, M. C. Hsieh, C. C. Chiu, T. Y. Hung, M. C. Yew, and K. N. Chiang "Interfacial Delamination Investigation between Copper Bumps in 3D Chip Stacking Package by Using the Modified Virtual Crack Closure Technique," MAM 2010, Mechelen, Belgium, Mar. 7-10, 2010.

參與計畫:

台達電與清華大學合作計畫書: 2009~2013

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蘇彥輔(Yen-Fu Su)

E-mail: yenfusu@gmail.com

相關著作(Publication)

Journal Papers

	P. C. Chen, Y. F. Su, S. Y. Yang, S. Y. Liang, and K. N. Chiang, "Determination of Initial Crack Strength of Silicon Die Using Acoustic Emission Technique," Journal of Electronic Materials, vol. 44, 2015, pp. 2497-2506
	P. C. Chen, Y. F. Su, S. Y. Yang, C. C. Lee, and K. N. Chiang, "Evaluation of Die Strength using Finite Element Method with Experiment Validation," IEEE Transactions on Components, Packaging, and Manufacturing Technology, Volume 4, July 2014, Pages 1152-1158
	C. F. Huang; Y. F. Su; C. B. Lin; K. N. Chiang, "Research on Efficiency Droop Mechanism and Improvement in AlGaInP Ultra-High-Brightness LEDs Using the Transient Measurement Method", Solid-State Electronics, Volume 120, 25 May 2014, Pages 182–187
	C. F. Huang, Y. F. Su, C. B. Lin, and K. N. Chiang,"Research on the degradation of AlGaInP Ultra High Brightness LEDs influenced by ohmic metal design," Microelectronic Engineering , Available online 29 July 2013, ISSN 0167-9317
	Chang-Chun Lee, Yen-Fu Su, Chih-Sheng Wu, and Kuo-Ning Chiang, "Investigation of interconnect design on interfacial cracking energy of Al/TiN barriers under a flexural load," Thin Solid Films, Volume 544, Pages 530–536, 1 October 2013
	Y. F. Su, S. Y. Yang, T. Y. Hung, C. C. Lee, and K. N. Chiang, "Light degradation test and design of thermal performance for high-power light-emitting diodes," Microelectronics Reliability, Volume 52, Issue 5, pp.794-803, 2012

Conference Papers

	L. L. Liao, T. Y. Hung, C. K. Liu, Y. F. Su and K. N. Chiang, "Study on configuration design of interconnection in high power module" EuroSimE 2015, Budapest, Hungary, April 20-22, 2015
	H. T. Yang, Y. F. Su and K. N. Chiang, "Research on Packing Effects of Three-axis SOI MEMS Accelerometer" EuroSimE 2015, Budapest, Hungary, April 20-22, 2015
	F. M. Hsu, Y. F. Su and K. N. Chiang, "Determination of the Junction Temperature of Gallium Nitride (GaN)-based High Power LED Under Thermal with Current loading Conditions" ICEP2015, Kyoto, Japan, April 15-17
	C. C. Yang, C. C. Tsai, Y. F. Su and K. N. Chiang, "Analysis of LED Wire Bonding Process Using Arbitrary Lagrangian - Eulerian and Equilibrium Mesh Smoothing Algorithm" ICEP2015, Kyoto, Japan, April 15-17
	T. L. Chou, C. C. Lee, H. N. Chiang, C. T. Lin, Y. F. Su, and K. N. Chiang, "Study on Thermal Induced Stress Hysteresis Behavior of Thin Film Sensor," ThinFilms 2014, Chongqing, China, Jul. 15-18, 2014
	H. J. Wang, H. A. Deng, S. Y. Chiang, Y. F. Su, and K. N. Chiang, "Development of a Feasible Simulation Methodology for Residual Stress Assessment of Multilayer Thin Film Structure," ThinFilm2014, Chongqing, China, Jul. 15-18, 2014
	Y. H. Yang, Y. F. Su, and K. N. Chiang, "Acceleration Factor Analysis of Aging Test on Gallium Nitride (GaN)-based High Power Light-emitting Diode (LED)," ITherm 2014, Orlando, USA, May 27-30, 2014
	Y. F. Su, C.T. Lin, T. Y. Kuo, and K. N. Chiang, "Structure design and reliability assessment of double-sided with double-chip stacking packaging," EuroSimE 2014, Gent, Belgien, April 7-9, 2014
	L.L. Liao, T. Y. Hung, C. K. Liua, Y. F. Su, and K. N. Chiang, "Study on configuration design of interconnection in high power module," EuroSimE 2014, Gent, Belgien, April 7-9, 2014
	K. C. Lin, C.C. Tsai, Y. F. Su, T. Y. Hung, K.N. Chiang, "Analysis of LED Wire Bonding Process Using Arbitrary Lagrangian-Eulerian and Explicit Time Integration Methods", iMPACT2013, Taipei,Taiwan, Oct 23-25, 2013
	Y. F. Su, C. T. Lin, T. Y. Kuo, and K. N. Chiang, "Development of Double-Sided with Double-Chip Stacking Structure using Panel Level Embedded Wafer Level Packaging," Electronic Components Technology Conference (ECTC 2013), Las Vegas, NV, USA, May 28-31, 2013
	C. F. Huang, Y. F. Su, C. B. Lin, and K. N. Chiang, "Research on the degradation of AlGaInP Ultra High Brightness LEDs influenced by ohmic metal design", Materials for Advanced Metallization Conference, MAM 2013, Leuven, Belgium, Mar. 10-13, 2013
	Y. F. Su, Y. H. Yang, W. K. Yang, and K. N. Chiang, "A Thermal Performance Assessment of Panel Type Packaging (PTP) Technology for High Efficiency LED," 14th International Conference on Electronics Materials and Packaging, December 13-16, 2012, Hong Kong.
	Y. J. Lee, Y. F. Su, T. Y. Hung, and K. N. Chiang, "Reliability Analysis of 3D IC Integration packaging under Drop Test Condition," iMPACT 2012, Taipei, Taiwan, October 24-26
	C. C. Lee, Y. F. Su, C. S. Wu, and K. N. Chiang, "Investigation of Interconnect Design on Interfacial Cracking Energy of Al/TiN Barriers under a Flexural Load," ThinFilms2012, Singapore, July 14-17
	C. F. Huang, Y. F. Su, S. Y. Yang, C. L. Hsu, N. C. Chen, and K. N. Chiang, "Quantum Efficiency Investigation at high Current Density of Ultra-High-Brightness LEDs," ITHERM 2012, San Diego, California, USA, May 30 - June 1
	P. C. Chen, Y. F. Su, S. Y. Yang, and K. N. Chiang, "Determination of Silicon Die Initial Crack Using Acoustic Emission Technique," iMPACT 2011, Taipei, Taiwan, October 19-21
	T. H. Kuo, Y. F. Su, C. J. Wu, and K. N. Chiang, "Stress/Stain Assessment and Reliability Prediction of Through Silicon Via and Trace Line Structures of 3D Packaging," EuroSimE 2011, Linz, Austria, April 18-20, 2011.
	Y. F. Su, S. Y. Yang, W. H. Chi and K. N. Chiang, "Light degradation prediction of high-power light-emitting diode lighting modules," in Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE), 2010 11th International Conference on, 2010, pp. 1-6.
	Y. F. Su; T. Y. Hung; S. Y. Yang; K. N. Chiang, “A Study on the Thermal Performance of a Chip-in-substrate-type LED Package Structure”, CPMT Symposium Japan, 2010 IEEE, 2010 , pp. 1 - 4.
	C. F. Huang; Y. F. Su; C. B. Lin; K. N. Chiang, "Research on Efficiency Droop Mechanism and Improvement in AlGaInP Ultra-High-Brightness LEDs Using the Transient Measurement Method", Solid State Electronics, Accepted and to be published

廖莉菱(Li-Ling Liao)

E-mail: powerzero0412@hotmail.com

相關著作(Publication)

Journal Papers

	L. L. Liao, T. Y. Huang, C. K. Liu, W. Li, M. J. Dai, and K. N. Chiang, "Electro-thermal finite element analysis and verification of power module with aluminum wire", Microelectronic Engineering, Volume 120, 25 May 2014, Pages 114–120
	T. Y. Hung, L. L. Liao, C. C. Wang, W. H. Chi, and K. N. Chiang, "Life Prediction of High Cycle Fatigue in Aluminum Bonding Wires under Power Cycling Test", IEEE Transactions on device and materials reliability, Available online 05 November 2013, ISSN 1530-4388.
	L. L. Liao, M. J. Dai, C. K. Liu, and K. N. Chiang, "Thermo-electric finite element analysis and characteristic of thermoelectric generator with intermetallic compound", Microelectronic Engineering, Volume 120, 25 May 2014, Pages 194–199

Conference Papers

	L. L. Liao, T. Y. Hung, C. K. Liu, Y. F. Su and K. N. Chiang, "Study on configuration design of interconnection in high power module" EuroSimE 2015, Budapest, Hungary, April 20-22, 2015
	L.L. Liao, T.Y. Hung, C.K. Liua, Y.F. Su, and K.N. Chiang, "Study on configuration design of interconnection in high power module," EuroSimE 2014, Gent, Belgien, April 7-9, 2014
	L. L. Liao, T. Y. Huang, C. K. Liu, W. Li, M. J. Dai, and K. N. Chiang, "Electro-thermal finite element analysis and verification of power module with aluminum wire", Materials for Advanced Metallization Conference, MAM 2013, Leuven, Belgium, Mar. 10-13, 2013
	L. L. Liao, M. J. Dai, C. K. Liu, and K. N. Chiang, "Thermo-electric finite element analysis and characteristic of thermoelectric generator with intermetallic compound", Materials for Advanced Metallization Conference, MAM 2013, Leuven, Belgium, Mar. 10-13, 2013
	L. L. Liao, M. J. Dai, C. K. Liu, J. Y. Chang and K. N. Chiang, " Development and analysis of the thermoelectric material with intermetallic compound," ICEP 2012, Tokyo, Japan, April 17-21
	H. H. Chang, L. L. Liao and K. N. Chiang, " External Stress Effect to Electromigration on Thermal Annealed and Residual Stress Controlled Aluminum Strip," ICEP2012, Tokyo, Japan, April 17-21

吳凱強(Kai-Chiang, Wu)

E-mail: kc_wu@tsmc.com

相關著作(Publication)

Journal Papers

K. C. Wu, and K. N. Chiang, " Characterization on Acceleration-Factor Equation for

Packaging-Solder Joint Reliability," Microelectronics Reliability, Accepted and to be published, 2016.

C. H. Lee, K. C. Wu, and K. N. Chiang, "A novel acceleration-factor equation for packaging solder joint," Journal of Mechanics, in press, 2016. (DOI:http://dx.doi.org/10.1017/jmech.2016.30)

K. C. Wu, S. Y. Lin, T. Y. Hung, and K. N. Chiang, "Reliability assessment of packaging solder joints under different thermal cycle loading rates," IEEE Transactions on Device and Materials Reliability, vol. 15, pp. 437-442, 2015.

Conference Papers

	K. C. Wu, C. H. Lee, and K. N. Chiang, “Characterization of thermal cycling ramp rate and dwell time effects on AF (Acceleration Factor) estimation,” ECTC 2016, Las Vegas, USA, May 31- June 3, 2016.
	K. C. Wu, S. Y. Lin and K. N. Chiang, "Investigation of strain rate effect on lifetime performance of wafer level CSP under different thermal cycling loading rate," IMPACT 2014, Taipei, Taiwan, October 22-24, 2014.
	K. C. Wu, and K. N. Chiang, “Investigation of solder creep behavior on wafer level CSP under thermal cycling loading,” ICEP 2014, Toyama, Japan, April 23-25, 2014.

張嘉誠 (Chia-Cheng, Chang)

博士班2019年畢

E-mail： cchiacheng@gmail.com

	C. C. Chang and K. N. Chiang, "Empirical High Cycle Fatigue Assessment Model of MEMS Devices", Journal of Electronic Packaging, Volume 142, 011005-1 to 10, March 2020.
	C. C. Chang, S.D. Lin and K.N. Chiang, "Development of a High Cycle Fatigue Life Prediction Model for Thin Flim Silicon Structures", Journal of Electronic Packaging, Volume140,Issue 3, September 2018.

Conference Papers

C. C. Chang, S. D. Lin and K. N. Chiang, "Empirical High Cycle Fatigue Life Prediction Model for Polysilicon MEMS", Materials for advanced metallization (MAM) 2018, Milan, Italy, March 18-21, 2018.

C. C. Chang, H. T. Yang, Y. F. Su, Y. T. Hong, and K. N. Chiang, "A Method to Compensate Packaging Effects on three-axis MEMS Accelerometer," ITherm 2016, Las Vegas, NV, USA, May 31- June 3, 2016

王保雄(Bao-Hsiong, Wang)

博士班2020年畢

Email： s 101033812@gmail.com

Journal Papers

P. H. Wang, Y. W. Huang, and K. N. Chiang, "Reliability Evaluation of Fan-out Type 3D Packaging-on-Packaging", Micromachines, 12(3), 295, https://doi.org/10.3390/mi12030295, Mar. 2021.

P. H. Wang, Y. C. Lee, C. K. Lee, H. H. Chang, and K. N. Chiang, "Solder Joint Reliability Assessment and Pad Size Studies of FO-WLP with Glass Substrate", IEEE Transactions on Device and Materials Reliability, Vol. 21, No. 1, pp. 96-101, DOI: 10.1109/TDMR.2021.3056054, March 2021.

P. L. Wu, P. H. Wang and K. N. Chiang, "Empirical Solutions and Reliability Assessment of Thermal Induced Creep Failure for Wafer Level Packaging,IEEE Transactions on Device and Material Reliability,Volume 19, Issue 1, Pages 126-132, March 2019.

Conference Papers

	P. H. Wang, A. Huang and K. N. Chiang ,"Design And Reliability Assessment of Stacked FAN-OUT Packaging", SMTA Pan Pacific Microelectronics Conference, Hawaii, USA, February 5-8, 2018.
	T. N Chang, A. Huang, K. C. Wu, P. L. Wu, Y. T. Shen, P. H. Wang and K.N. Chiang, “Reliability Evaluation of I/O Pad Size Effect of FO-WLCSP”, 2018IMPACT, Oct 24- Oct 26, Taipei, Taiwan.

黃昱瑋(Yu-Wei, Huang)

博士班2023年畢

E-mail： fionhuang123@gmail.com

Journal Papers

	Y. W. Huang, K. N. Chiang, “Study of shear locking effect on 3D solder joint reliability analysis”, Journal of Mechanics, Volume 38, 2022, pp. 176–184.
	C. F. Yu, Y. W. Huang, T. Y. Ouyang, S. F. Cheng, H. H. Chang, C. C. Hsiao , “Suppression Strategy for Process-induced Warpage of Novel Fan-out Wafer Level Packaging”, Microelectronics Reliability,136, pp.114683(1)-114683(10), 20220901
	M. K. Shih, Y.W. Huang, G. S. Lin, “Next-Generation High-Density PCB Development by Fan-Out RDL Technology”, IEEE Transactions on Device and Materials, Reliability, 10.1109/ TDMR.2022.3174604, (2022), pp.296-305,2022051
	H. W. Hu, Y. W. Huang, Y. C. Tsai, M. K. Shih, K. N. Chen “Hybrid Soldering 2.3D Assembly With High Reliability and Low Cost, Electron Devices Society”, Volume 10, September 2022, IEEE Journal of the Electron Devices Society, pp.791-796.
	P. H. Wang, Y.W. Huang and K. N. Chiang, “Reliability Assessment of PoP Fan-Out With Glass Substrate”, Micromachines, 2021, 12, 295, pp.1-14.

Conference Papers

	Y. W. Huang, K. N. Chiang, “Thermal Assessment for Chiplets System-in-Package”, International Microsystems, Packaging, Assembly and Circuits Technology Conference, (2022).
	C. F. Yu, Y. W. Huang, T. Y. Ouyang, S. F. Cheng, C. C. Hsiao, “Evaluation on Process-induced Warpage of Novel Fan-Out Wafer Level Packaging using TSV Interposer-First Technology, International Conference on Electronics Packaging”, International Conference on Electronics Packaging, (2022), pp 195-196.
	Y. W. Huang, K. N. Chiang, “Study of Shear Locking Effect on 3D Solder Joint Reliability Analysis”, International Microsystems, Packaging, Assembly and Circuits Technology Conference, (2021)
	Y. W. Huang, K. N. Chiang, “Reliability Assessment of Thermal Induced Creep Failure for WLCSP”, International Microsystems, Packaging, Assembly, Circuits Technology, (2020)

碩士班

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張郡文

碩士班2000年畢

畢業論文：

異向導電膠接合型態之翻轉式晶片的製程模擬與可靠度研究
　

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劉振南

碩士班2000年畢

畢業論文：

無底膠新型覆晶封裝結構之設計與可靠度分析

$描述: 描述: 描述: 描述: 描述: D:\www\csml\members\graduated\der.gif$

林永得

碩士班2000年畢

畢業論文：

晶圓級/覆晶形態封裝之設計與可靠度分析

$描述: 描述: 描述: 描述: 描述: D:\www\csml\members\graduated\S-M Shee.jpg$

許世民

碩士班2001年畢

畢業論文：

三維無底膠覆晶結構非線性有限元熱應力/應變分析

$描述: 描述: 描述: 描述: 描述: D:\www\csml\members\graduated\C-T Peng.jpg$

彭治棠

碩士班2001年畢

畢業論文：

電子構裝及微機電系統之多層板結構理論分析與實驗驗證

$描述: 描述: 描述: 描述: 描述: D:\www\csml\members\graduated\C-C Lee.jpg$

李昌駿

碩士班2002年畢

畢業論文：

具發泡式緩衝層之晶圓級封裝設計與可靠度分析

$描述: 描述: 描述: 描述: 描述: D:\www\csml\members\graduated\G-L Chen.jpg$

陳永儒

碩士班2002年畢

畢業論文：

覆晶凸塊應用於光學被動對位

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廖啟銘

碩士班2002年畢

畢業論文：

邊射型雷射自動對位控制研究

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顧曉東

碩士班2002年畢

畢業論文：

光收發射器之光纖陣列模組可靠度分析

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陳正斌

碩士班2003年畢

畢業論文：

BGA光收發模組之可靠度與耦合效率分析

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孫銘鴻

碩士班2003年畢

畢業論文：

微卡榫應用於光纖與光波導耦合之機制研究

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江欣怡

碩士班2004年畢

畢業論文：

電熱式微致動器之結構設計與熱傳分析

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劉興治

碩士班2003年畢

畢業論文：

以發泡式基板為應力緩衝層之晶圓級封裝之三維結構設計與可靠度分析

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張家豪

碩士班2004年畢

畢業論文：

應變矽於奈米結構之分析與設計

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廖偉全

碩士班2004年畢

畢業論文：

使用大撓度理論探討奈米探針之結構行為及其參數化設計
　

專利:

具有光波導之掃描探針式/進場光學式顯微鏡用之探針（中華民國專利，證號I237276）

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周展延

碩士班2005

畢業論文：

使用原子-連體力學法於奈米尺度結構之力學性質研究

Homepage: g923770

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蔣信男

碩士班2006年畢

畢業論文:

矽質微型壓阻式壓力感測器之遲滯現象研究

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朱振宏

碩士班2006年畢

畢業論文:

矽質微型壓阻式壓力感測器封裝效應之研究

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施建仲

碩士班2007年畢

畢業論文:

鋁合金輪圈撞擊測試之電腦模擬分析

E-mail: sirius@webmail.pme.nthu.edu.tw

Homepage: g943762

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沈傑

碩士班2007年畢

畢業論文:

矽質微型壓阻式壓力感測器之熱遲滯現象研究

E-mail: carb@webmail.pme.nthu.edu.tw

Homepage: g943781

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魏修平

碩士班2007年畢

畢業論文:

具金屬載板之三維堆疊式嵌板型晶圓级封裝其結構可靠度暨熱傳分析

E-mail: shopmanwei@gmail.com

Homepage: g943775

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黃昭荏

碩士班2007年畢

畢業論文:

奈米尺度下具點缺陷金屬晶體結構之力學性質研究

E-mail: cjh@webmail.pme.nthu.edu.tw

Homepage: g943767

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鄧宏安

碩士班2008年畢

畢業論文:

高功率氮化鎵發光二極體於雷射剝離後之晶圓翹曲分析

E-mail:kof2051@yahoo.com.tw

Homepage:g9533562

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江室瑩

碩士班2008年畢

畢業論文:

類晶圓級多晶片模組式封裝之散熱特性與內埋金屬導線可靠度分析

E-mail:g9533571@oz.nthu.edu.tw

Homepage:g9522571

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洪端佑

碩士班2008年畢

畢業論文:

晶片尺寸封裝電路板層級衝擊測試可靠度分析

E-mail:g9533554@oz.nthu.edu.tw

Homepage:g9433554

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紀偉豪

碩士班2009年畢

畢業論文:

高功率發光二極體照明模組之散熱特性分析

E-mail:g9633558@oz.nthu.edu.tw

Homepage:g9633558

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佐野雅文

碩士班2009年畢

畢業論文:

晶片尺寸封裝於板層級掉落測試之不確定性與可靠度分析

E-mail:g9633555@oz.nthu.edu.tw

Homepage:g9633555

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許仕逸

碩士班2009年畢

畢業論文:

應用金屬接合與直通矽晶穿孔技術於三維晶片堆疊封裝之可靠度分析

E-mail:g9633571@oz.nthu.edu.tw

Homepage:g9633571

蘇彥輔

碩士班2010年畢

畢業論文:

高功率發光二極體之散熱設計與光衰壽命測試

E-mail:g9733550@oz.nthu.edu.tw

Homepage:g9733550

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郭廷鑫

碩士班2010年畢

畢業論文:

三維式晶片堆疊封裝於直通矽晶穿孔結構與銅導線之可靠度分析

E-mail:g9733552@oz.nthu.edu.tw

Homepage:g9733552

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王寧遠

碩士班2010年畢

畢業論文:

高聚光型太陽能電池模組於熱循環測試下之壽命預測

E-mail:g9733559@oz.nthu.edu.tw

Homepage:g9733559

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魏守勤

E-mail: u940771@oz.nthu.edu.tw

王涵融

E-mail: hahazoon@hotmail.com

相關著作:

Conference Papers

H. J. Wang, H. A.Deng, S. Y. Chiang, and K. N. Chiang "Thin Film Residual Stress Assessment of Capacitive MEMS Microphones Using Process Modeling Technology," in InterPACK 2011, Jul 6-8, Portland, Oregon, USA, 2011

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陳珮綺

E-mail: u940702@oz.nthu.edu.tw

相關著作:

Conference Papers

P. C. Chen, S. Y. Yang, K. N. Chiang "Determination and Verification of Silicon Die Strength Using Ball-Breaker Test," in InterPACK 2011, Jul 6-8, Portland, Oregon, USA, 2011

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江室瑩

E-mail: g9533571@oz.nthu.edu.tw

相關著作:

Journal Papers

	S. Y. Chiang, T. L. Chou, Z. H. Shih, H. F. Hong, and K. N. Chiang, "Life prediction of HCPV under thermal cycling test condition," Microelectronic Engineering, vol. 88, pp. 785-790, 2011.
	T. Y. Hung, S. Y. Chiang, C. J. Huang, C. C. Lee, and K. N. Chiang, "Thermal-mechanical behavior of the bonding wire for a power module subjected to the power cycling test," Microelectronics Reliability, in press.

Conference Papers

	T. Y. Hung, S. Y. Chiang, C. J. Huang, C. C. Wang, K. C. Lu, and K. N. Chiang, "Dwell Time Effect and Thermal Fatigue Life Assessment of Power Module," 13th International Conference on Electronics Materials and Packaging, 3 pp. 2011, Kyoto, Japan
	T. Y. Hung, S. Y. Chiang, C. J. Huang, C. C. Lee, K. N. Chiang, "Thermal-mechanical behavior of the bonding wire for a power module subjected to the power cycling test," 22nd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), October 3-7, 2011, Bordeaux, France.
	S. Y. Chiang, S. Y. Yang, C. Y. Chou, M. C. Yew, and K. N. Chiang, "Reliability Analysis of Copper Interconnections of System-in-Packaging Structure using Finite Element Method," presented at the 2008 International Conference on Electronic Packaging Technology & High Density Packaging, Vols 1 and 2, 2008.
	S. Y. Yang, S. Y. Chiang, C. Y. Chou, M. C. Yew, K. N. Chiang, and Ieee, "Reliability Analysis of Copper Interconnections of System-in-Packaging," presented at the Impact: 2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference, 2009.
	N. Y. Wang, S. Y. Chiang, T. L. Chou, H. L. Lee, and C. Kuo-Ning, "Life prediction of high concentration photovoltaic modules subjected to thermal cycling test," presented at the Microsystems Packaging Assembly and Circuits Technology Conference (IMPACT), 2010 5th International, 2010.
	T. Y. Hung, S. Y. Chiang, C. Y. Chou, C. C. Chiu, and K. N. Chiang, "Thermal design and transient analysis of insulated gate bipolar transistors of power module," presented at the Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2010 12th IEEE Intersociety Conference on, 2010.
	S. Y. Chiang, T. L. Chou, Z. H. Shih, H. F. Hong and K. N. Chiang "Non-Uniform Thickness Effect of Die Bonding Interface in High-Concentration Photovoltaic Module," EMAP 2009, Penang, Malaysia, Dec 1-3, 2009.
	S. Y. Chiang, T. Y. Hung, Ray Hsing and K. N. Chiang, "Temperature Dependent Current Crowding Analysis of Insulated Gate Bipolar Transistor," ICEP2010, Sapporo, Hokkaido, Japan, May 12-14, 2010.
	S. Y. Chiang, T. Y. Hung, H. C. Ou, and K. N. Chiang, "Electro-Thermal Analysis of the Insulated Gate Bipolar Transistor Module Subjected to Power Cycling Test Using Specified Boundary Condition Technology," EuroSimE 2011, Linz, Austria, April 18-20, 2011.
	H. J. Wang, H. A.Deng, S. Y. Chiang, and K. N. Chiang "Thin Film Residual Stress Assessment of Capacitive MEMS Microphones Using Process Modeling Technology," in InterPACK 2011, Jul 6-8, Portland, Oregon, USA, 2011

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賴致廷

E-mail: u9533213@oz.nthu.edu.tw

Conference Papers

C. T. Lai, T. Y. Hung, and K. N. Chiang, "Investigation on the Effect of Surface Roughness on the Fracture Strength of SCS", EuroSimE 2012, Lisbon, Portugal, April 16-18

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