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Ph. D. Students

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Chang K. C.

graduated in 2003

Email: kcchange@tsmc.com

Thesis:

Study of Effects of Cu Stud Design and IMC Growth on the Reliability of Micro-Electronic Devices

Papers:

1. Growth Analysis of Interfacial Delamination of Plastic Ball Grid Array Package During Solder Reflow(PDF)

2. FAILURE PREDICTION IN PLASTIC BALL GRID ARRAY ELECTRONIC PACKAGING (PDF)

3. HYGROTHERMAL STRESS ANALYSIS OF PLASTIC BALL GRID ARRAY PACKAGE DURING SOLDER REFLOW (PDF)

4. 塑封球柵陣列電子構裝之界面脫層裂縫尖端應力強度因子分析(PDF)

5. Effect of Cu Stud on Solder Ball Shear Strength

6. Impact of Aging on Solder Ball Shear Strength

7. Solder Joint Reliability Analysis of a Wafer-level CSP Assembly with Cu Studs Formed on Solder Pads

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Chen K. M.

graduated in 2003

Email: kuoming_chen@umc.com

Thesis:

A Study of Microelectronics Probing Depth and Electormigration Effect of Solder Bump.

Papers:

1. PBGA 與T²-BGA之共面性研究(PDF)

2. Impact of probing procedure on flip chip reliability

3. Thermal Resistance Analysis and Validation of Flip Chip BGA Packages

4. Developing an Analytic Methodology to Predict Probing Depth in Integrated Circuit Structures

5. 以解析法預測積體電路元件之針測壓痕深度

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Lin J. C.

graduated in 2003

Email:

Thesis:

Design, Reliability and Thermal Analysis of Micro-Electronic Devices Packaging

Papers:

1. Thermal/Machnical analysis of novel c-TSOP using nonlinear FEM method (PDF)

2. A study of Factors Affecting Solder Joint Fatigue Life ofThermally Enhanced Ball Grid Array Assembly

3. Thermal/mechanical analysis of novel C-TSOP using nonlinear FEM method

4. Design and Analysis of Ceramic-TSOP Package

5. A Full-Scale 3D Finite Element Analysis for No-underfill Flip Chip Package

6. Investigation of Thermal Effect of Packaged CMOS Compatible Pressure Sensor

7. Design and Analysis of Wafer-Level CSP with Double-Pad-Structure

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Liu C. M.

graduated in 2004

Email:

Thesis:

A Study of Effects of Solder Joint Layout, Geometry and Manufacturing Parameters on the Reliability of Micro-Electronic Devices

Papers:

Solder Shape Design and Thermal Stress/Strain Analysis of Flip Chip Packaging Using Hybrid Method (PDF)
Analysis of Reflow Geometry for TheHybrid-Pad-Shapes System of Ball Grid Array Packages(PDF)
Solder Reflow Prediction of Hybrid Pad Packaging System (PDF)
Pad Design and Reliability Analysis for Flip Chip Packaging.
Design and Thermal Stress/Strain Analysis of Cast-In Dry Liner.
Solder Bumps Layout Design and Reliability Enhancement of Wafer Level Packaging.

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Yuan C. A. (Cadmus)

graduated in 2005

E-mail: cayuan@ccca.nctu.edu.tw

Thesis:

Investigation of nano-scaled structural mechanics using the clustered atomistic-continuum method

Homepage: http://ccca.nctu.edu.tw/~cayuan/cayuan/index.htm

Journal Paper

1. K. N. Chiang and C. A. Yuan, "An Overview of Solder Bump Shape Prediction Algorithms with Validations", IEEE Transactions on Advanced Packaging, Vol.24, No.2, pp.158-162, May, 2001 (SCI/EI)

2. C. A. Yuan and K. N. Chiang, " Micro to Macro Thermo-Mechanical Simulation of Wafer Level Packaging," ASME trans. on Journal of Electronic Packaging, vol 125, no. 4, pp. 576-581, Dec., 2003(SCI/EI)

Conference Paper

1. Yuan, C. A. and Chiang, K. N.,"Micro to Macro Thermo-Mechanical Simulation of Wafer Level Packaging", EuroSimE2001 Conference (IEEE,EI), April 9-11 2001, Paris

2. 袁長安、林基正、劉昌明、張國欽、江國寧，「微機電/電子構裝參數分析之人機介面」，2001 Taiwan User Conf., 翡翠灣，台北，台灣。

3. Yuan, C. A., Liu, H., Sun, M. H., Chiang, K. N., "Design, analysis and validation of vertical probing technology," EuroSimE2003 international Conference, 2003, Aix-en-Provence, France.

4. Yuan, C. A. and Chiang, K. N., "Investigation of dsDNA stretching meso-mechanics using finite Element Method”, 2004 Nanotechnology Conference, March 7-11, 2004, Boston, Massachusetts, U.S.A.

5. Yuan, C. A. and Chiang, K. N., "Investigation of dsDNA stretching meso-mechanics using LS-DYNA", 2004 LSTC User's Conf.,Dearbone,DI, U.S.A.

6. Yuan, C. A., Han, C. N. and Chiang, K. N., “Design and Analysis of Novel WLCSP Structure”, EuroSIME2004 International Conference, May 9-May 12, 2004, Brussels, Belgium.

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Peng C. T.

graduated in 2005

E-mail:d907710@oz.nthu.edu.tw

Thesis:

Design, Analysis and Experiment Validation of Structural Reliability and Microwave Signal Response of Advanced Microsystems Pachages

Homepage: d907710

Papers

Parametric Design and Reliability Analysis of Wire Interconnect Technology Wafer Level Packaging, ASME Transaction of Electronic Package, Vol.124, No. 3, pp. 234-239, Sep. 2002
Parametric Reliability Analysis of No-Underfill Flip Chip Package, IEEE Transactions on Components and Packaging Technologies, Vol. 24, No. 4, pp. 635-640, Dec. 2001
Reliability Analysis and Design for the Fine-pitch Flip Chip BGA Packaging, IEEE Transactions on Component and Packaging Technologies
Analysis and Validation of Thermal and Packaging Effects of a Piezoresistive Pressure Sensor, Journal of the Chinese Institute of Engineers (JCIE)
Performance and Package Effect of a Novel Piezoresistive Pressure Sensor Fabricated by Front-Side Etching Technology, Sensor and Actuator Journal (SNA)
Overview of Multilayered Thin Film Theories for MEMS and Electronic Packaging Applications, 8th Intersociety Conference on Thermal and Thermommechanical phenomena in Electronic Systems, pp. 1058-1065, May 30-Jun. 1, 2002, San Diego, CA, United States
Investigation of Thermal Effect of Packaged CMOS Compatible Pressure Sensor, 2002 ASME International Mechanical Engineering Congress and Exposition, pp. 505-512, Nov. 17-22, 2002, New Orleans, LA, United States
The Reliability Analysis and Structure Design for the Fine Pitch Flip Chip BGA Package, 4th International Conference on Thermal & Mechanical Simulation and Experiments in Microelectronics and Microsystems, pp. 413-420, Mar. 30-Apr. 2, 2003, Aix-en-Provence, France
Analysis and Validation of Sensing Sensetivity of a Piezoresistive Pressure Sensor, 2003 International Electronic Packaging Technical Conference and Exhibition, pp. 225-231, Jul 6-11, 2003, Haui, HI, United States
A Novel Silicon Base Piezoresistive Pressure Sensor Using Front Side Etching Process, pp. 79-86, 2003 ASME International Mechanical Engineering Congress, Nov 15-21 2003, Washington, DC, United States
Design and Analysis of the CMOS Compatible Pressure Sensor Using Flip Chip and Flex Circuit Board Technologies, pp. 43-49, 2003 ASME International Mechanical Engineering Congress, Nov 15-21 2003, Washington, DC, United States
Design, Fabrication and Comparison of Lead-Free/Eutectic Solder Joint Reliability of Flip Chip Package, 5th international conference on thermal, mechanical and thermo-mechanical simulation and experiments in micro-electronics and icro-systems, pp. 149-156, Brussels, Belgium, May 10-12, 2004
Experimental Characterization and Mechanical Behavior Analysis on Intermetallic Compounds of 96.5Sn-3.5Ag and 63Sn-37Pb Solder Bump with Ti-Cu-Ni UBM on Copper Chip, 54th Electronic Components and Technology Conference, Las Vegas, United States

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Lin C. T. (Ethan)

graduated in 2006

E-mail: d883783@oz.nthu.edu.tw

Thesis:

Investigation of nanoscale single crystal IV-A group mechanical properties using atomistic-continuum mechanics(ACM)

Homepage: d883783

Journal Paper

Chiang, K. N., Chang C. W. and Lin C. T., “Process Modeling and Thermal/Mechanical Behavior of ACA/ACF Type Flip-Chip Package,” TRANSATIONS of the ASME, Journal of Electronic Package, Vol. 123, pp. 331-337, 2001.

Lin, C. T. and Chiang, K. N., “Reliability Analysis of Flip Chip Packages Using the Contact Finite Element Method,” Journal of the Chinese Institute of Engineers, Vol. 27, No. 2, pp.165-172, 2004.

Conference Papers

Chiang, K.N. Chang C. W. and C. T. Lin, “Process and Reliability Simulation of Flip Chip using ACF", Proceeding of EPTC 2000 (IEEE, EI), pp. 110-116, Dec. 2000, Singapore.

Lin, C. T. and Chiang, K. N., "Reliability Analysis of Flip Chip Packages Using the Contact Finite Element Method", Published (CD-ROM) at Annual Meeting of CSME, Nov. 8, 2001, Taipei.

Peng, C. T., Lin, J. G., Lin, C. T and Chiang, K. N., "Investigation of Thermal Effect of Packaged CMOS Compatible Pressure Sensor", Published at 2002 ASME Intl. Mechanical Engineering Congress and Exposition, Symposium on Microelectronic Manufacturing, Reliability, and Quality Assurance Testing, Nov. 17-22, 2002, New Orleans, USA.

Lin, C. T., Peng, C. T., Lin, J. C. and Chiang, K. N., “Analysis and Validation of Sensing Sensitivity of a Piezoresistive Pressure Sensor”, Published at InterPACK2003 (IEEE/ASME), June 30 – July 5, Hawaii, USA.

J. Y. Chen, C. T. Lin, W. C. Liao, H. C. Su, C. H. Ysai and K. N. Chiang, “A New Nano-Probe Using Micro Assembly Transfer”, Published at 3rd Cross-Strait Workshop on Nano Science & Technology, April 27 – 29, 2004, HuaLian, Taiwan.

C.T. Lin, W.C. Liao, J.Y. Chen, H.C. Su and K.N. Chiang , “Design and Analysis of Nano-Probe of AFM Using Large Deflection Theory “, 3rd Cross-Strait Workshop on Nano Science & Technology, April 27 – 29, 2004, HuaLian, Taiwan.

Chen, J. Y., Lin, C. T., Liao, W. C., Su, H. C., Tsai, C. H. and Chiang, K. N., “A New Nano-Probe Using Micro Assembly Transfer”, Published at First International Nano Bio-Packaging Workshop, March 22-23, 2004, Atlanta.

C. T. Lin, W. C. Liao, J. Y. Chen, H. C. Su and K. N. Chiang, “Design and Analysis of a Nano-Probe for the AFM based on the Small/Large Deflection Theory,” Published at 2004 ASME Intl. Mechanical Engineering Congress and Exposition, Nov. 13-19, 2004, Anaheim, USA.

W. C. Liao, C. T. Lin and K. N. Chiang, “Experiment Validation of a Nano-Probe for the AFM based on the Large Deflection Theory,” Published (CD-ROM) at Annual Meeting of CSME, Nov. 11, 2004, KaoHsiung.

C. T. Lin and K. N. Chiang,” Thermal and Mechanical Responses of Thermomechanical Microprobe for High Density Storage Technology,” published at Microelectronics, MEMS, and Nanotechnology 2005 (SPIE), Brisbane, Australia, Dec. 11–14 2005.

C. T. Lin and K. N. Chiang,”Investigation of Nano-Scale Single Crystal Silicon Using the Atomistic-Continuum Mechanics with Stillinger-Weber Potential Function,” published at NanoSingapore 2006 (IEEE), Singapore, Jan. 10-13, 2006.

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Lee C. C.

graduated in 2006

E-mail: d917716@oz.nthu.edu.tw

Thesis:

Investigation of Micro Electronic Devices Reliability Using Interfacial Crack Growth Prediction Methodology

Homepage: d917716

Journal Papers

1. Lee, C. C., Chiang, K. N., Chen, W. K., and Chen, R. S., “Design and Analysis of Gasket Sealing of Cylinder Head under Engine Operation Conditions,” Finite Elements in Analysis and Design, Vol. 41, No. 11-12, pp. 1160-1174, Jun. 2005.

2. Lee, C. C., Chiang, K. N., “Design and Reliability Analysis of a Novel Wafer Level Package with Stress Buffer Mechanism,” Accepted and to be published at Journal of the Chinese Institute of Engineers, 2005.

3. Lee, C. C., Liu, H. C., and Chiang, K. N., "3D Structure Design and Reliability Analysis of Wafer Level Package with Stress Buffer Mechanism," Accepted and to be published at IEEE Transactions on Component and Packaging Technologies, 2006.

4. Lee, C. C., Chiang, K. N., Chen, W. K., and Chen, R. S., 2003, “Design and Analysis of Gasket Sealing for Cylinder Head in 2.0L Engine Operation,” Paper #G225, The 27^th Conference on Theoretical and Applied Mechanics, Tainan, Taiwan, Dec. 12-13.

5. Lee, C. C., Liu, H. C., and Chiang, K. N., 2004, “3D Structure Design and Reliability Analysis of Wafer Level Package with Bubble-Like Stress Buffer Layer,” 9^th Intersociety Conference on Thermal and Thermomechanical phenomena in Electronic Systems (ITHERM 2004), Las Vegas, USA, Jun. 1-4.

6. Lee, C. C., Chang, S. M., and Chiang, K. N., 2004, “Design of Double Layer WLCSP Using DOE with Factorial Analysis Technology,” 6th IEEE Electronics Packaging Technology Conference (EPTC 2004), pp.776-781, Singapore, Dec. 8-10.

7. Liu, C. M., Lee, C. C., and Chiang, K. N., 2005, “Solder Joints Layout Design and Reliability Enhancement of Wafer Level Packaging,”6th IEEE EuroSimE2005 conference, pp.234-241, Berlin, Germany, Apr. 18-20.

8. Lee, Chien Chen, Lee, Chang Chun, and Chiang, Kou Ning, 2005,“Thermal Performance and Solder Joint Reliability for Board Level Assembly of Modified Leadframe Module,”6th IEEE EuroSimE2005 conference, pp.553-558, Berlin, Germany, Apr. 18-20.

9. Lee, Chang Chun, Lee, Chien Chen, Cheng, Chih Yuan, and Chiang, Kou Ning, 2005,“Robust Design for the Reliability Optimization of WLCSP Using Response Surface Methodology,”IMAPS-TAIWAN 2005 International Technical Symposium, pp.209-214, Taipei, Taiwan, Jun. 23-25.

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Kuo C. T.

graduated in 2007

Thesis:

Investigation of the Mechanical Stress-Induced Shift and Variation of Electrical Characteristics in the Analogic Device and MOSFETs

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Han C. N.

E-mail: d927715@oz.nthu.edu.tw

Homepage: d927715

Thesis:

Investigation of bionano-scaled structural mechanics using atomistic-continuum mechanics method

Papers

C. A. Yuan, C. N. Han, M. C. Yew, C. Y. Chou and K. N. Chiang, "Design, Analysis and Development of Novel Three-Dimensional Stacking WLCSP," accepted by IEEE Transaction of Advanced Packaging.
C. A. Yuan, C. N. Han and K. N. Chiang , “Design and Analysis of Novel WLCSP Structure”, EuroSIME2004 International Conference, May 9-May 12, 2004, Brussels, Belgium.
C. A. Yuan, C. N. Han and K. N. Chiang, "Atomistic to Continuum Mechanical Investigation of ssDNA and dsDNA using Transient Finite Element Method," Inter-Pacific Workshop on Nanoscience and Nanotechnology, Nov. 22-Nov. 24, City University of Hong Kong, Hong Kong SAR.

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Lee C. C.

E-mail: d927719@oz.nthu.edu.tw

Homepage: d927719

Thesis

Investigation of Electromigration Characteristic in SnAg3.0Cu0.5 Flip Chip Interconnection and the External Mechanical Stress Impact of Al Thin Film

Paper

l Chien Chen Lee, Kuo Ming Chen, Frank Kuo, and Kou Ning Chiang, “Electromigration Study of Sn3.0Ag0.5Cu Flip Chip Solder Bumps”, Accepted and to be published at The 2006 Pan Pacific Microelectronics Symposium, Jan. 17 - 19, 2006, Hawaii, USA.

l Chang Chun Lee, Chien Chen, Lee, Chin-Yuan, Cheng, Kuo Ning Chiang, “Structural Design for Enhancing WLCSP Reliability by Using Response Surface Method”, submitted to IEEE Transactions on Advanced Packaging, 2005

l Chang Chun Lee, Chien Chen, Lee, Chin-Yuan, Cheng, Kuo Ning Chiang, “Robust Design for the Reliability Optimization of WLCSP Using Response Surface Methodology”, Published at The IMAPS-Taiwan 2005 Technical Symposium, June 23 – 25, 2005, Taipei, Taiwan

l Chien Chen Lee, Chang Chun Lee, Chip Tang Peng and Kou Ning Chiang, “Thermal Performance and Solder Joint Reliability for Board Level Assembly of Modified Leadframe Module”, Published at The 6th IEEE EuroSimE international conference (IEEE/ASME), April 18-20, 2005, Berlin, Germany

l Chien Chen Lee and Kou Ning Chiang, “RF Substrate Via Relative Issue Discussion - Via and Ni/Au Surface Layer Crack”, Published at The 7th VLSI Packaging Workshop of Japan (IEEE/CMPT), Nov. 30 - Dec. 2, 2004, Kyoto, Japan.

l William R. Yueh, Chien Chen Lee and Alex B.L. Wu, "Finite Element Analysis of Novel Substrate Design for High performance and Cost Reduction Stacked Die CSP", Published at 27th Annual International Electronics Manufacturing Technology Symposium (IEEE/CMPT), July 17-18, 2002, San Jose, CA, USA

l Chien Chen Lee and Jimmy C.M. Chen, "A Study of Thermomechanical Behavior and Reliability on uBGA package", Published at the 6^th ABAQUS User’s Conference, Oct. 29-30, 2001, Taiwan

l Chien Chen Lee and Kei G.D. Lou, "Design Characteristics of High Performance and Reduced Cost Chip Scale Package - μBGA," Published at 10^th Internal Flotherm Users Conference, Oct. 2001, Amsterdam, Netherlands

Patent

l Taiwan Patent No. I236,124

l Taiwan Patent No. I227,051

l Taiwan Patent No. 204,838

l Taiwan Patent No. 204,164

l Taiwan Patent Application No. 93130206

l US Patent Application No. 10/922,422

l US Patent Application No. 10/964,542

l US Patent Application No. 11/023,749

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Yew M. C. (Jason)

E-mail: jasonyew@webmail.pme.nthu.edu

Homepage: d923768

Thesis:

Design, Structural Reliability Assessment, and Electromigration Evaluation for the Advanced Microelectronic Packages

Project:

1. 清華大學/育霈科技計畫合作案, The Reliability Analysis of Novel Slide-able Cu Trace Wafer Level Chip Scale Package (2005.06 迄今)

2. 台積電/清華大學從事半導體合作研究計畫, Interfacial stress, adhesion, crack propagation simulation of multilayer and stacked structure of low-k chip (2005.02 迄今)

3. 工業技術研究院電子工業研究所自主性前瞻計畫, 5X/16X Product Design and Development Procedure (2004.01~2004.12)

4. 4. 工業技術研究院電子工業研究所專利搜尋：Stretchable Circuit 相關結構、設計 (2005.08 迄今)

Conference paper:

	M. C. Yew, C. Yuan, C. N. Han, C. S. Huang, W. K. Yang, K.N. Chiang, "Factorial Analysis of Chip-on-Metal WLCSP Technology with Fan-Out Capability," Accepted and to be presented in IPFA2006 International Conference, July 3-7, 2006, Singapore.
	Ming-Chih Yew, Yu- Hua Chen, Wen-Kung Yang, Kuo-Ning Chiang,"Using FEM-based Method for Sensitivity Design of Chip-in-Substrate-Package,"Accepted and to be presented in IMAPS-Taiwan 2006 Technical Symposium, June 28 - July 1, 2006, Taipei World Trade Center, Taipei, Taiwan.
	Ming-Chih Yew, Ching-Shun Huang, Wen-Kung Yang and Kou-Ning Chiang,"Reliability and Characterization of Novel WLCSP with Fan-Out Capability,"Accepted and to be presented in IMAPS-Taiwan 2006 Technical Symposium, June 28 - July 1, 2006, Taipei World Trade Center, Taipei, Taiwan.
	C. Yuan, G. Q. Zhang, C. S. Huang, C. H. Yu, C. C. Yang, W. K. Yang, M. C. Yew, C. Y. Chou and K. N. Chiang, "Design, Experiment and Analysis of the Solder on Rubber (SOR) structure of WLCSP," Proceedings of the 7th International conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSIME2006, Como (Milano), Italy, April 23 - 26, 2006, pp. 619-625.
	C. Yuan, G. Q. Zhang, C. S. Huang, C. H. Yu, C. C. Yang, W. K. Yang, M. C. Yew, C. N. Han and K. N. Chiang, "Design and Analysis of a novel fan-out WLCSP structure," AProceedings of the 7th International conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSIME2006, Como (Milano), Italy, April 23 - 26, 2006, pp. 297-304.
	Ming-Chih Yew, Chang-Ann Yuan, Yu- Hua Chen, Wen-Kung Yang, Kuo-Ning Chiang, "Sensitivity Design of Chip-in-Substrate-Package Using DOE with Factorial Analysis Technology," Proceedings of the 7th International conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSIME2006, Como (Milano), Italy, April 23 - 26, 2006, pp. 589-595.
	C. Yuan, C. N. Han, C. Y. Chou, M. C. Yew and K. N. Chiang, "Simulation of unzipping dsDNA mechanical response using Clustered Atomistic-Continuum Method." ICCES'05 International Conference, Dec. 1- 6, 2005, in Chennai, India.
	Ming-Chih Yew, Chang-Chun Lee, Shu-Ming Chang and Kuo-Ning Chiang, "Reliability Analysis of a New Soft Joint Protection Technology Using in WLCSP," 2005 Taiwan ANSYS Users Conference, Oct. 23-25, 2005, Hualien, Taiwan, pp. 5-27~5-34
	Ming-Chih Yew, Chang-Chun Lee and Kuo-Ning Chiang, "A NOVEL WLCSP USING SOFT JOINT PROTECTION TECHNOLOGY," 2005 International Electronic Packaging Technical Conference and Exhibition, InterPACK 2005, July 17-22, 2005, San Francisco, CA, USA
	Chang-Chun Lee, Hsin-Chih Liu, Ming-Chih Yew and Kuo-Ning Chian, 2004, “3D Structure Design and Reliability Analysis of Wafer Level Package with Bubble-Like Stress Buffer Layer,” 9th Intersociety Conference on Thermal and Thermomechanical phenomena in Electronic Systems (ITHERM 2004), Las Vegas, USA, Jun. 1-4.

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Chiu C. C. (Luke)

E-mail: d937709@oz.nthu.edu.tw

Homepage: d937709

Thesis:

Study on the Multilevel Interconnection Delamination and the Mechanical Stress induced Efficiency Change of the Carrier Mobility

Conference Paper :

Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Kuo-Ning Chiang, Terry Ku and Kenny Cheng "Reliability Analysis and Factorial Design of Lead-Free Flip Chip Package Using THE Finite Element Method", Proceedings of IPACK2005, International Electric Packaging Technical Conference and Exhibition, July 17-22, San Francisco, California, USA

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Chou C. Y. (James)

E-mail: chk@webmail.pme.nthu.tw

Homepage: g923770

Thesis:

Research of Dynamic Analysis and Impact Life Prediction Theory for Wafer Level Package Subjected to Drop Impact

Papers:

	C. Y. Chou, T. Y. Hung, M. C. Yew, W. K. Yang, D. C. Hu, M. C. Tsai, C. S. Huang, and K. N. Chiang, "Investigation of Stress-buffer-enhanced Package Subjected to Board-level Drop Test," EuroSimE2008, 20-23 April, Freiburg im Breisgau, Germany.
	S. Y. Chiang, C. Y. Chou, M. C. Yew, and K. N. Chiang, "Reliability Analysis of Copper Interconnection in System-in-package Structure," International Conference on Electronics Materials and Packaging (EMAP2007), November 19-22, 2007, Daejeon, Korea.
	C. J. Huang, C. Y. Chou, C. J Wu, and K. N. Chiang, "Investigation of the mechanical properties of nano-scale metallic crystal structural with point defects," European Nano System 2007 (ENS'07), December 3-4, 2007, Paris, France
	M. C. Yew, C. Y. Chou, and K. N. Chiang, "Reliability assessment for solders with a stress buffer layer using ball shear strength test and board-level finite element analysis." Microelectronics Reliability, Vol. 47, pp. 1658-1662, 2007.
	C. Y. Chou, C. J. Wu, H. P. Wei, M. C. Yew, C. C. Chiu, and K. N. Chiang, "Thermal management on hot spot elimination / junction temperature reduction for high power density system in package structure," InterPACK 2007, July 8-12, 2007, Vancouver, BC, Canada.
	Chan-Yen Chou, Chung-Jung Wu, Hsiu-Ping Wei, Ming-Chih Yew, Chien-Chia Chiu and Kuo-Ning Chiang, "Thermal Management on Hot Spot Elimination / Junction Temperature Reduction for High Power Density RF Multi-chip Module," Thermal Stress 2007, June 4-7, 2007, Taipei, Taiwan.
	C. N. Han, C. Y. Chou, and K. N. Chiang, "Investigation of Mechanical Strength of The Nanoshell of Bacteriophage Phi-29," NSTI Nanotech2007, May20-24, 2007, Santa Clara, USA.
	C. N. Han, C. Y. Chou, and K. N. Chiang, "Investigation of dsDNA Molecule Mechanical Behavior Using Atomistic Continuum Mechanics Method," NSTI Nanotech2007, May20-24, 2007, Santa Clara, USA.
	C. J. Wu, C. Y. Chou, C. N. Han, and K. N. Chiang, "Simulation and Validation of CNT Mechanical Properties – The Future Interconnection Material.", Electronic Components and Technology Conference (ECTC 2007), May 30 - Jun. 1, Reno, USA.
	Chun-Te Lin, Chan-Yen Chou, and Kuo Ning Chiang, "Estimation and validation of mechanical properties of single crystal silicon by atomic-level numerical model," Accepted in International Conference on Experimental Mechanics (ICEM13), Alexandroupolis, Greece, July1-6, 2007.
	Chan-Yen Chou, Chung-Jung Wu, Hsiu-Ping Wei, Ming-Chih Yew, Chien-Chia Chiu and Kuo-Ning Chiang, THERMAL MANAGEMENT ON HOT SPOT ELIMINATION / JUNCTION TEMPERATURE REDUCTION FOR HIGH POWER DENSITY SYSTEM IN PACKAGE STRUCTURE, accepted in 2007 International Electronic Packaging Technical Conference and Exhibition, InterPACK 2007, Vancouver, Canada, July 8-12, 2007.
	Chun-Te Lin, Chan-Yen Chou, Chao-Jen Huang, and Kuo-Ning Chiang, "Validation of mechanical properties of the nanoscale single crystal IV-A group material by Atomistic-Continuum Mechanics Model," The 30th Conference of Theoretical and Applied Mechanics, 2006 12/15~12/16, Taiwan.
	M. C. Yew, C. Y. Chou, C. S. Huang, W. K. Yang, K. N. Chiang, "The Solder on Rubber (SOR) Interconnection Design and Its Reliability Assessment Based on Shear Strength Test and Finite Element Analysis," Journal of Microelectronics Reliability, Vol. 46, 2006, pp. 1874-1879
	Cadmus Yuan, Chan-Yen Chou, Cheng-Nan Han, Ming-Chih Yew and Kou-Ning Chiang,"12" to 8" wafer transformationn technique using novvel glass WLCSP structure," Proceedings of the IMAPS-Taiwan 2006 Technical Symposium, June 28 - July 1, 2006, Taipei World Trade Center, Taipei, Taiwan.
	C. Yuan, G. Q. Zhang, C. S. Huang, C. H. Yu, C. C. Yang, W. K. Yang, M. C. Yew, C. Y. Chou and K. N. Chiang, "Design, Experiment and Analysis of the Solder on Rubber (SOR) structure of WLCSP," Proceedings of the 7th International conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSIME2006, Como (Milano), Italy, April 23 - 26, 2006, pp. 619-625.
	Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Chan-Yen Chou and Kuo-Ning Chiang , "Reliability Impact of Highly Temperature-Dependent Underfill Material to the Lead-Free Flip Chip Package," EuroSimE2006 international Conference, 2006,in Como (Milano), Italy.
	Chung-Jung Wu, Chan-Yen Chou, Cheng-Nan Han, Kuo-Ning Chiang, “Investigation of Carbon Nanotube Mechanical Properties Using The Atomistic-Continuum Mechanics Method.”, NSTI Nanotech 2006, Boston, Massachusetts ( USA), 2006.
	C. N. Han, C. Y. Chou, C. J. Wu and K. N. Chiang, “Investigation of ssDNA Backbone Molecule Mechanical Behavior Using Atomistic-Continuum Mechanics Method”, NSTI 2006 Nanotechnology Conference, May 7-11, 2006, Boston, Massachusetts, U.S.A.
	C. Yuan, C. N. Han, C. Y. Chou, M. C. Yew and K. N. Chiang, "Simulation of unzipping dsDNA mechanical response using Clustered Atomistic-Continuum Method." ICCES'05 International Conference, Dec. 1-6, 2005, in Chennai, India.
	Chan-Yen Chou, Cadmus Yuan, Chung-Jung Wu and Kuo -Ning Chiang, "Numerical Simulation of the Mechanical Properties of Nanoscale Metal Clusters Using the Atomistic-Continuum Mechanics Method.", European Nano System 2005, 14-16 December 2005, Paris, France.
	K. N. Chiang , C.A. Yuan, C. N. Han, C. Y. Chou and Yujia Cui,"Mechanical Characteristic of ssDNA/dsDNA Molecule Under External Loading", Appl. Phy. Lett., 88, 023902, 2006, also published in the January 23, 2006 issue of Virtual Journal of Nanoscale Science & Technology.
	C. H. Chang, C. Y. Chou, C. N. Han, C. T. Peng, K. N. Chiang, “ Local-Strain Effect of the SiNx/Si Stacking and Nano-Scale Triple Gate Si/SiGe MOS Transistor”, published at Microelectronics, MEMS, and Nanotechnology 2005 (SPIE), Brisbane, Australia, Dec. 11–14 2005.
	C. Y. Chou, C. A. Yuan, and K. N. Chiang, "Investigation of Nano-scaled Material Behavior Using Atomistic-Continuum Mechanics Method." The 22nd National Conference on Mechanical Engineering, CSME, Nov. 25-26, C11-006, 2005.
	C. A. Yuan , C. N. Han, M. C. Yew, C. Y. Chou and K. N. Chiang, “Design, Analysis and Development of Novel Three-Dimensional Stacking WLCSP,” IEEE Transaction of Advanced Packaging, Vol 28, No. 3, pp. 387-396, Aug. 2005.
	C. H. Chang, C. Y. Chou, C. T. Peng, C. N. Han, and K. N. Chiang, “Investigation of Local-Strain Effect of the Nano-Scale Triple Gate Si/SiGe and SiNx/Si Stacking MOS Transistor.” NSTI Nanotechnology Conference, May 8-12, 2005, Anaheim, California, U.S.A.

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Chou T. L. (Denny)

E-mail: tsunglin0502@webmail.pme.nthu.tw

Homepage:

Thesis:

Fabrication Process Modeling and Reliability Improvement of High-Brightness LEDs

描述: d9533807

Wu C. J.

E-mail: d9533807@oz.nthu.edu.tw

Homepage: d9533807 More about me!

Thesis:

Application of Interfacial Strength Simulation in Three-Dimensional Chip Stacking Electronic Packaging and Four-Point Bending Delamination Test

Publication:

Journal Papers:

	K. N. Chiang, C. Y. Chou, C. J. Wu, C. J. Huang, and M. C. Yew, "Analytical solution for estimation of temperature-dependent material properties of metals using modified Morse potential," Computer Modeling in Engineering and Science, Vol. 37, pp. 85-96, 2008.
	C. C. Chiu, C. J. Wu, C. T. Peng, K. N. Chiang, T. Ku, and K. Cheng, "Failure life prediction and factorial design of lead-free flip chip package," Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers, Vol.30, No. 3, pp. 481-490, 2007.
	K. N. Chiang, C. Y. Chou, and C. J. Wu, and C. A. Yuan, "Prediction of The Bulk Elastic Constant of Metals Using Atomic-Level Single-Lattice Analytical Method" Appl. Phys. Lett. 88, 171904, 2006

Conference Papers:

	C. J. Wu, M. C. Hsieh, and K. N. Chiang, "Die-Cracking Evaluation of Silicon Chip Covered with Polymer Film for 3D Chip Stacking Packages," International Conference on Electronics Packaging, ICEP 2009, Kyoto, Japan, Apr. 14-16, 2009.
	C. J. Wu, M. C. Hsieh, and K. N. Chiang, "Strength Evaluation of Silicon Die for 3D Chip Stacking Packages Using ABF as Dielectric and Barrier Layer in Through-Silicon Via,", Materials for Advanced Metallization Conference (MAM 2009), Grenoble, France, Mar. 8-11, 2009.
	C. J. Wu, C. Y. Chou, C. N. Han, and K. N. Chiang, "Simulation and Validation of SWCNT Mechanical Properties." Taiwan ANSYS/Fluent Conference, 2008, Taipei, Taiwan.
	H. P. Wei, M. C. Yew, C. J. Wu, and K. N. Chiang, "Reliability and Thermal Assessment of Stacked Chip-on-Metal Panel Based Package (PBPTM) with Fan-Out Capability," 2nd Electronics System-Integration Technology Conference, ESTC 2008, 01-04 September, London, England.
	Ming-Chih Yew, Chung-Jung Wu and Kuo-Ning Chiang, "Trace Line Failure Analysis and Characterization of the Panel Base Package (PBPTM) Technology with Fan-Out Capability," Proceedings of the 11th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITherm 2008, pp. 862-869, May 28 -31, 2008, Florida, USA.
	C. J. Wu, C. Y. Chou, C. N. Han, and K. N. Chiang, "Estimation and Validation of Elastic Modulus of Carbon Nanotubes Using Nano-Scale Tensile and Vibrational Analysis.", International Conference on Computational & Experimental Engineering and Sciences 2008 (ICCES'08), 16-21 March, 2008, Honolulu, Hawaii, USA.
	C. J. Huang, C. Y. Chou, C. J. Wu, and K. N. Chiang, "Investigation of the mechanical properties of nano-scale metallic crystal structural with point defects," European Nano System 2007 (ENS'07), December 3-4, 2007, Paris, France
	C. Y. Chou, C. J. Wu, H. P. Wei, M. C. Yew, C. C. Chiu, and K. N. Chiang, "Thermal management on hot spot elimination / junction temperature reduction for high power density system in package structure," InterPACK 2007, July 8-12, 2007, Vancouver, BC, Canada.
	Chan-Yen Chou, Chung-Jung Wu, Hsiu-Ping Wei, Ming-Chih Yew, Chien-Chia Chiu and Kuo-Ning Chiang, "Thermal Management on Hot Spot Elimination / Junction Temperature Reduction for High Power Density RF Multi-chip Module," Thermal Stress 2007, June 4-7, 2007, Taipei, Taiwan.
	C. J. Wu, C. Y. Chou, C. N. Han, and K. N. Chiang, "Simulation and Validation of CNT Mechanical Properties – The Future Interconnection Material.", Electronic Components and Technology Conference (ECTC 2007), May 30 - Jun. 1, Reno, USA.
	Chung-Jung Wu, Chan-Yen Chou, Cheng-Nan Han, Kuo-Ning Chiang, "Numerical Simulation of the Mechanical Properties of Carbon Nanotube Using the Atomistic-Continuum Mechanics.", European Nano System 2006, 14-15 December 2006, Paris, France.
	Chung-Jung Wu, Chan-Yen Chou, Cheng-Nan Han, Kuo-Ning Chiang, “Investigation of Carbon Nanotube Mechanical Properties Using The Atomistic-Continuum Mechanics Method.”, NSTI Nanotech 2006, Boston, Massachusetts ( USA), 2006.
	Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Chan-Yen Chou and Kuo-Ning Chiang , "Reliability Impact of Highly Temperature-Dependent Underfill Material to the Lead-Free Flip Chip Package," EuroSimE2006 international Conference, 2006,in Como (Milano), Italy.
	Chan-Yen Chou, Cadmus Yuan, Chung-Jung Wu and Kuo -Ning Chiang, "Numerical Simulation of the Mechanical Properties of Nanoscale Metal Clusters Using the Atomistic-Continuum Mechanics Method.", European Nano System 2005, 14-16 December 2005, Paris, France.
	Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Kuo-Ning Chiang, Terry Ku and Kenny Cheng "Reliability Assessment of Lead-Free Flip Chip Package Using Factorial Design Methodology", Taiwan ANSYS User Conference, 2005
	Chien-Chia Chiu, Chung-Jung Wu, Chih-Tang Peng, Kuo-Ning Chiang, Terry Ku and Kenny Cheng "Reliability Analysis and Factorial Design of Lead-Free Flip Chip Package Using THE Finite Element Method", Proceedings of IPACK2005, International Electric Packaging Technical Conference and Exhibition, San Francisco, California, USA, 2005

Project：

	ITRI Project – Validation and Analysis of the Interfacial Reliability of 3DIC-SiP (2009.01~Now)
	Taiwan TFT LCD Association, TTLA (ITRI) – "Composite Bump" Patents Search (2006.07~Now)
	ITRI Project – Validation and Application of Strain Energy Release Rate of the Interconnect Via in System-in-Packaging (2008.01~2008.12)
	ITRI Project – Crack Model of the Interconnect Via in System-in-Packaging (2007.01~2007.12)

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Zhang S.H.

E-mail: mikechang@itri.org.tw

Thesis:

Investigation of Thermal and Stress Coupling Effects on Electromigration in Metal Strip

Publication:

Journal Papers

C. C. Chiu, H. H. Chang, C. C. Lee, C. C. Hsia, and K. N. Chiang, "Reliability of interfacial adhesion in a multi-level copper/low-k interconnect structure," Microelectronics Reliability, vol. 47, pp. 1506-1511, Sep-Nov 2007.

Conference Papers

	H. H. Chang, J. H. Huang, C. W. Chiang, Z. C. Hsiao, H. C. Fu, C. H. Chien, Y. H. Chen, W. C. Lo, and K. N. Chiang, “Process Integration and Reliability Test for 3D Chip Stacking with Thin Wafer Handling Technology,” in Electronic Components and Technology Conference, May 31-Jun. 3, Florida, US, 2011.
	W. L. Tsai, H. H. Chang, C. H. Chien, J. H. Lau, H. C. Fu, C. W. Chiang, T. Y. Kuo, Y. H. Chen, R. Lo and M. J. Kao, “How to Select Adhesive Materials for Temporary Bonding and De-Bonding of 200mm and 300mm Thin-Wafer Handling for 3D IC Integration?,” in Electronic Components and Technology Conference, May 31-Jun. 3, Florida, US, 2011.
	Sheng-Ho Huang*, Chun-Hsing Lee, Hung-Lien Hu, Mu-Tao Chu, Jen-Hao Yeh, Yuan-Chin Chen, Yu-Ming Huang, Chao-Kai Hsu, Hsiang-Hung Chang and Huan-Chun Fu, “A Low Cost Rigid-Flex Opto-electrical Link for Mobile Devices,” in International Microsystems, Packaging, Assembly and Circuits Technology Conference, Oct. 20-22, Taipei, Taiwan, 2010.
	H. H. Chang, J. H. Huang, C. W. Chiang, Z. C. Hsiao, H. C. Fu, Y. H. Chen and K. N. Chiang, “Process Integration for 3D Chip Stacking with Thin Wafer Handling Technology,” in Materials for Advanced Metallization Conference, Mar. 7-10, Mechelen, Belgium, 2010.
	H. H. Chang, Y. C. Shih, Z. C. Hsiao, C. W. Chiang, Y. H. Chen, and K. N. Chiang, “3D Stacked Chip Technology Using Bottom-up Electroplated TSVs,” in Electronic Components and Technology Conference, May 26-29, San Diego, CA, US, 2009.
	T. Y. Kuo, Y. C. Shih, Y. C. Lee, H. H. Chang, Z. C. Hsiao, C. W. Chiang, S. M. Li, Y. J. Hwang, C. T. Ko, Y. H. Chen, “Flexible and Ultra-Thin Embedded Chip Package,” in Electronic Components and Technology Conference, May 26-29, San Diego, CA, US, 2009
	H. H. Chang, Y. C. Shih, C. K. Hsu, Z. C. Hsiao, C. W. Chiang, Y. H. Chen, and K. N. Chiang, “TSV Process Using Bottom-up Cu Electroplating and its Reliability Test,” in Electronics System-Integration Technology Conference, September 1-4, Greenwich, UK, 2008.
	S. G. Lee, C. H. Lee, C. C. Lu, F. Y. Cheng, K. Y. Shen, S. H. Huang, L. C. Shen, S. M. Chang, H. H. Chang, H. C. Fu, P. Tien, M. T. Chu, and Y. J. Chan, “Recent Trend of Optical Circuit Board in Taiwan,” in Polymers and Adhesives in Microelectronics and Photonics, January 16-18, Odaiba, Tokyo, Japan, 2007.
	W. C. Lo, S. M. Chang, Y. H. Chen, J. D. Ko, T. Y. Kuo, H. H. Chang, Y. C. Shih, “3D Chip-to-Chip Stacking with Through Silicon Interconnects,” in International Symposium on VLSI Technology, Systems and Applications, April 23-25, Hsinchu, Taiwan, 2007.
	H. H. Chang, W. C. Lo, L. C. Shen, H. C. Fu, Y. C. Lee, and S. M. Chang, “Interconnection of Flexible Electronic-Optical Circuit Board Module,” in International Microsystems, Packaging, Assembly and Circuits Technology Conference, October 18-20, Taipei, Taiwan, 2006
	L. C. Shen, W. C. Lo, H. H. Chang, H. C. Fu, Y. C. Lee, S. M. Chang, Y. C. Chen, and W. Y. Chen, “Flexible Electronic-Optical Local Bus Modules to the Board-to-Board, Board-to-Chip, and Chip-to-Chip Optical Interconnection,” in Electronic Components and Technology Conference, May 31- June 3, Lake Buena Vista, Florida, US, 2005.
	L. C. Shen, W. C. Lo, H. H. Chang, H. C. Fu, Y. C. Lee, Y. C. Chen, S. M. Chang, W. Y. Chen, and M. C. Chou, “Characterization of Organic Multi-mode Optical Waveguides for the Electro-Optical Printed Circuit Board (EOPCB),” in Electronics Packaging Technology Conference, December 8-10, Singapore, 2004.
	W. C. Lo, L. C. Shen, H. H. Chang, H. C. Fu, Y. C. Chen, S. M. Chang, Y. C. Lee, W. Y. Chen, M. C. Chou, “Polymeric Waveguides on Rigid and Flexible PCB,” in Electronic Components and Technology Conference, June 1-4, Las Vegas, US, 2004.

Patents

	Taiwan Patent No. I324058
	Taiwan Patent No. I332790
	China Patent No. ZL200710112678.9
	US Patent No. 7,663,231
	US Patent Application No. 12/155,715
	US Patent Application No. 12/500,780
	Taiwan Patent Application No. 96125246
	Taiwan Patent Application No. 97120592
	Taiwan Patent Application No. 97129949
	Taiwan Patent Application No. 98140290
	China Patent Application No. 200810213229.8
	China Patent Application No. 201010606570.7
	Taiwan Patent Application No. 99140809
	US Patent Application No. 13/037,372

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Huang C.J.

E-mail: d9633834@oz.nthu.edu.tw

Journal Papers

	K. N. Chiang, C. Y. Chou, C. J. Wu, C. J. Huang, and M. C. Yew, "Analytical Solution for Estimation of Temperature-Dependent Material Properties of Metals Using Modified Morse Potential," Cmes-Computer Modeling in Engineering & Sciences, vol. 37, pp. 85-96, Nov 2008.
	C. C. Chiu, C. J. Huang, S. Y. Yang, C. C. Lee, and K. N. Chiang, "Investigation of the delamination mechanism of the thin film dielectric structure in flip chip packages," Microelectronic Engineering, vol. 87, pp. 496-500, Mar 2010.
	C. Y. Chou, T. Y. Hung, C. J. Huang, and K. N. Chiang, "Development of Empirical Equations for Metal Trace Failure Prediction of Wafer Level Package Under Board Level Drop Test," Ieee Transactions on Advanced Packaging, vol. 33, pp. 681-689, Aug 2010.
	C. J. Huang, C. J. Wu, H. A. Teng, and K. N. Chiang , "A Robust Nano-Mechanics Approach for Tensile and Modal Analysis Using Atomistic-Continuum Mechanics Method" Computational Materials Science, vol.50, pp.2245-2248, 2011.
	T. Y. Hung, S. Y. Chiang, C. J. Huang, C. C. Lee, and K. N. Chiang, "Thermal-mechanical behavior of the bonding wire for a power module subjected to the power cycling test," Microelectronics Reliability, in press.

Conference Papers

	T. Y. Hung, C. J. Huang, C. C. Lee, C. C. Wang, K. C. Lu, and K. N. Chiang, "Thermal Cycling Period Effect of Fatigue Life of the Power Module," Materials for Advanced Metallization Conference, MAM 2012, Grenoble, France, Mar. 11-14, 2012.
	C. J. Huang, T. Y. Hung, K. N. Chiang, "Analysis of the Mechanical Properties of Si/SiGe Heterostructure using Atomistic-continuum Mechanics with Constraint Equations,"APMC-10, ICONN 2012 & ACMM-22, Perth, WA Australia Feb. 5-9, 2012.
	T. Y. Hung, S. Y. Chiang, C. J. Huang, C. C. Wang, K. C. Lu, and K. N. Chiang, "Dwell Time Effect and Thermal Fatigue Life Assessment of Power Module," 13th International Conference on Electronics Materials and Packaging, 3 pp. 2011, Kyoto, Japan
	T. Y. Hung, S. Y. Chiang, C. J. Huang, C. C. Lee, K. N. Chiang, "Thermal-mechanical behavior of the bonding wire for a power module subjected to the power cycling test," 22nd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), October 3-7, 2011, Bordeaux, France.
	C. J. Huang, C.J. Wu, H.A. Teng, and K.N. Chiang, "Research on Multi-Scale Structural Analysis using the Atomistic-Continuum Equivalent Mechanics," CSWNST-8, Hong Kong, Dec. 19-22, 2010.
	C. J. Huang, C. J. Wu, H. A. Teng, K. N. Chiang, “Carbon nanotubes structural mechanics using the atomistic-continuum mechanics and equivalent methods” ACCM-7, Taipei, Taiwan, Nov. 15-18, 2010.
	C. J. Huang, C. J. Wu, H. A. Teng, and K. N. Chiang "A Robust Nano-Mechanics Approach for Tensile and Modal Analysis Using Atomistic-Continuum Mechanics Method," ICONN 2010, Sydney, Australia, Feb 22-26, 2010.
	M. Sano, C. Y. Chou, T. Y. Hung, S. Y. Yang, C. J. Huang, and K. N. Chiang, "Reliability and parametric study on chip scale package under board-level drop test," 4th IMPACT, Taipei, Taiwan, Oct. 21-23, 2009.
	C. Y. Chou, C. J. Huang, M. Sano, and K. N. Chiang, "Metal trace impact life prediction model for stress buffer enhanced package," 17th European Microelectronics and Packaging Conference & Exhibition (EMPC2009), Rimini, Italy, June 15-18, 2009.
	C. J. Huang, C. Y. Chou, K. N. Chiang, “Dynamic study and structure enhancement of small outline dual-in-line memory module”, International Conference on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE2009), Delft, Netherlands, April 27-29, 2009.
	C. C. Chiu, C. J. Huang, S. Y. Yang, C. C. Lee, and K. N. Chiang, "Investigation of the delamination mechanism of the thin film dielectric structure in flip chip packages" Materials for Advanced Metallization Conference (MAM 2009), Grenoble, France, Mar. 8-11, 2009.
	C. J. Huang, C. Y. Chou, C. J Wu, and K. N. Chiang, "Investigation of the mechanical properties of nano-scale metallic crystal structural with point defects," European Nano System 2007 (ENS'07), Paris, France, Dec. 3-4, 2007.
	H. P. Wei, M. C. Yew, C. J. Huang, and K. N. Chiang, "Failure mode and thermal performance analysis of stacked panel level package (PLP)," InterPACK 2007, Vancouver, BC, Canada, July 8-12, 2007.
	C. T. Lin, C. Y. Chou, C. J. Huang, and K. N. Chiang, "Validation of mechanical properties of the nanoscale single crystal IV-A group material by Atomistic-Continuum Mechanics Model," The 30th Conference of Theoretical and Applied Mechanics, Taiwan, Dec. 15-16, 2006.

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Yang S.Y.

E-mail: d9633805 @oz.nthu.edu.tw

Journal Papers

	T. L. Chou, S. Y. Yang, and K. N. Chiang, “Overview and applicability of residual stress estimation of film-substrate structure,” Thin Solid Films,” Volume 519, Volume 519, Issue 22, pp. 7883-7894, 2011.
	T. L. Chou, S. Y. Yang, C. J. Wu, C. N. Han, and K. N. Chiang, “Measurement and simulation of interfacial adhesion strength between SiO2 thin film and III-V material,” Microelectronics Reliability, Volume 51, Issue 9-11, pp. 1757-1761, 2011.
	T. L. Chou, S. Y. Yang, and K. N. Chiang, “Overview and Applicability ofResidual Stress Estimation of Film-Substrate Structure,” Thin Solid Films,Vol. 519, Issue 22, pp. 7883-7894, 2011
	Y. F. Su, S. Y. Yang, T. Y. Hung, C. C. Lee, and K. N. Chiang, "Light degradation test and design of thermal performance for high-power light-emitting diodes," Microelectronics Reliability, in press
	W. H. Chi, T. L. Chou, C. N. Han, S. Y. Yang, and K. N. Chiang, "Analysis of Thermal and Luminous Performance of MR-16 LED Lighting Module," Ieee Transactions on Components and Packaging Technologies, vol. 33, pp. 713-721, Dec 2010.
	C. C. Chiu, C. J. Huang, S. Y. Yang, C. C. Lee, and K. N. Chiang, "Investigation of the delamination mechanism of the thin film dielectric structure in flip chip packages," Microelectronic Engineering, vol. 87, pp. 496-500, Mar 2010.
	C. Y. Chou, T. Y. Hung, S. Y. Yang, M. C. Yew, W. K. Yang, and K. N. Chiang, "Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact," Microelectronics Reliability, vol. 48, pp. 1149-1154, Aug-Sep 2008.
	T. L. Chou, C. F. Huang, C. N. Han, S. Y. Yang, and K. N. Chiang, "Fabrication process simulation and reliability improvement of high-brightness LEDs," Microelectronics Reliability, vol. 49, pp. 1244-1249, Sep-Nov 2009.
	T. L. Chou, S. Y. Yang, C. J. Wu, C. N. Han, and K. N. Chiang, “Measurement and simulation of interfacial adhesion strength between SiO2 thin film and III-V material,” Microelectronics Reliability, in press.

Conference Papers

	C. F. Huang, Y. F. Su, S. Y. Yang, C. L. Hsu, N. C. Chen, and K. N. Chiang, "Quantum Efficiency Investigation at high Current Density of Ultra-High-Brightness LEDs," ITHERM 2012, San Diego, California, USA, May 30 - June 1
	P. C. Chen, Y. F. Su, S. Y. Yang, and K. N. Chiang, "Determination of Silicon Die Initial Crack Using Acoustic Emission Technique," iMPACT 2011, Taipei, Taiwan, October 19-21
	T. L. Chou, S. Y. Yang, C. J. Wu, C. N. Han, and K. N. Chiang, “Measurement and simulation of interfacial adhesion strength between SiO2 thin film and III-V material,” ESREF 2011, Bordeaux, France, Oct. 3-7, 2011.
	S. Y. Chiang, S. Y. Yang, C. Y. Chou, M. C. Yew, and K. N. Chiang, "Reliability Analysis of Copper Interconnections of System-in-Packaging Structure using Finite Element Method," presented at the 2008 International Conference on Electronic Packaging Technology & High Density Packaging, Vols 1 and 2, 2008.
	M. Sano, C. Y. Chou, T. Y. Hung, S. Y. Yang, and K. N. Chiang, "Uncertainty and Reliability Analysis of Chip Scale Package Subjected to Board-level Drop Test," presented at the Eurosime 2009: Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2009.
	M. Sano, C. Y. Chou, T. Y. Hung, S. Y. Yang, C. J. Huang, K. N. Chiang, "Reliability and Parametric Study on Chip Scale Package Under Board-Level Drop Test," presented at the Impact: 2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference, 2009.
	S. Y. Yang, S. Y. Chiang, C. Y. Chou, M. C. Yew, K. N. Chiang, "Reliability Analysis of Copper Interconnections of System-in-Packaging," presented at the Impact: 2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference, 2009.
	S. Y. Yang, T. L. Chou, C. F. Huang, C. J. Wu, C. L. Hsu, and K. N. Chiang, "Strength determination of light-emitting diodes and chip structure design," in Microsystems Packaging Assembly and Circuits Technology Conference (IMPACT), 2010 5th International, 2010, pp. 1-4.
	S. Y. Yang, T. L. Chou, C. F. Huang, C. J. Wu, C. L. Hsu, and K. N. Chiang, "Determination of maximum strength and optimization of LED chip structure," in Electronic System-Integration Technology Conference (ESTC), 2010 3rd, 2010, pp. 1-5.
	Y. F. Su, S. Y. Yang, W. H. Chi, and K. N. Chiang, "Light degradation prediction of high-power light-emitting diode lighting modules," in Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE), 2010 11th International Conference on, 2010, pp. 1-6.
	C. Y. Chou, T. Y. Hong, M. Sano, S. Y. Yang, and K. N. Chiang, "Investigation of Influences of PCB on Board-level Drop Test by Dynamic Simulation and Modal Analysis," presented at the Microsystems, Packaging, Assembly & Circuits Technology Conference, 2008. IMPACT 2008. 3rd International, 2008.
	H. A. Deng, S. Y. Yang, C. N. Han, T. L. Chou, and K. N. Chiang "Warpage Analysis of High Power InGaN Light Emitting Diodes after Laser Lift-off," EMAP 2009, Penang, Malaysia, Dec 1-3, 2009.
	W. H. Chi, T. L. Chou, C. N. Han, S. Y. Yang, and K. N. Chiang, "Analysis of Thermal Performance for High Power Light Emitting Diodes Lighting Module", International Conference on Electronics Packaging (ICEP 2009),Kyoto, Japan, April 14-16, 2009
	C. Y. Chou, T. Y. Hung, S. Y. Yang, M. C. Yew, W. K. Yang, and K. N. Chiang, "Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact," ESREF2008, 30 Sep. - 03 Oct., Maastricht, Netherland.
	P. C. Chen, S. Y. Yang, K. N. Chiang "Determination and Verification of Silicon Die Strength Using Ball-Breaker Test," in InterPACK 2011, Jul 6-8, Portland, Oregon, USA, 2011

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Huang C. F.

E-mail: Huangjanfu@hotmail.com

Journal Papers

	C. F. Huang, Y. F. Su, C. B. Lin, and K. N. Chiang,"Research on the degradation of AlGaInP Ultra High Brightness LEDs influenced by ohmic metal design," Microelectronic Engineering 2013, accepted and to be published.
	T. L. Chou, C. F. Huang, C. N. Han, S. Y. Yang, and K. N. Chiang, "Fabrication Process Simulation and Reliability Improvement of High- brightness LEDs," Microelectronics Reliability, Volume 49, Issue 9-11, pp. 1244-1249, 2009.
	T. L. Chou, C. F. Huang, C. N. Han, S. Y. Yang, and K. N. Chiang, "Fabrication process simulation and reliability improvement of high-brightness LEDs," Microelectronics Reliability, vol. 49, pp. 1244-1249, Sep-Nov 2009.

Conference Papers

	C. F. Huang, Y. F. Su, C. B. Lin, and K. N. Chiang,"Research on the degradation of AlGaInP Ultra High Brightness LEDs influenced by ohmic metal design," Leuven, Belgium, March 10-13, 2013.
	C. F. Huang, Y. F. Su, S. Y. Yang, C. L. Hsu, N. C. Chen, and K. N. Chiang, "Quantum Efficiency Investigation at high Current Density of Ultra-High-Brightness LEDs," ITHERM 2012, San Diego, California, USA, May 30 - June 1
	S. Y. Yang, T. L. Chou, C. F. Huang, C. J. Wu, C. L. Hsu, and K. N. Chiang "Strength Determination of Light-emitting diodes and Chip Structure Design," IMPACT2010, Taipei, Taiwan, Oct 20-22, 2010.
	S. Y. Yang, T. L. Chou, C. F. Huang, C. J. Wu, C. L. Hsu, and K. N. Chiang "Determination of Maximum Strength and Optimization of LED Chip Structure," ESTC2010, Berlin, Germany, Sep 14-16, 2010.
	C. N. Han, T. L. Chou, C. F. Huang, and K. N. Chiang, "Sappire-removed induced the deformation of high power InGaN light emitting diodes," EuroSimE2008, Freiburg im Breisgau, Germany, April 20-23, 2008.

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Hung T. Y.

E-mail:g9533554@oz.nthu.edu.tw

Journal Papers

	C. J. Huang, T. Y. Hung, and K. N. Chiang, " The Mechanical Properties of Carbon Nanotubes Ropes Using Atomistic-Continuum Mechanics and the Equivalent Methods," CMC: Computers, Materials, & Continua, 2013
	T. Y. Hung, C. J. Huang, C. C. Lee, C. C. Wang, K. C. Lu, and K. N. Chiang, " Investigation of Solder Crack Behavior and Fatigue Life of the Power Module on Different Thermal Cycling Period," has been accepted for publication in Microelectronic Engineering
	Y. F. Su, S. Y. Yang, T. Y. Hung, C. C. Lee, and K. N. Chiang, "Light degradation test and design of thermal performance for high-power light-emitting diodes," Microelectronics Reliability, in press
	C. Y. Chou, T. Y. Hung, C. J. Huang, and K. N. Chiang, "Development of Empirical Equations for Metal Trace Failure Prediction of Wafer Level Package Under Board Level Drop Test," Ieee Transactions on Advanced Packaging, vol. 33, pp. 681-689, Aug 2010.
	C. Y. Chou, T. Y. Hung, S. Y. Yang, M. C. Yew, W. K. Yang, and K. N. Chiang, "Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact," Microelectronics Reliability, vol. 48, pp. 1149-1154, Aug-Sep 2008.
	T. Y. Hung, S. Y. Chiang, C. J. Huang, C. C. Lee, and K. N. Chiang, "Thermal-mechanical behavior of the bonding wire for a power module subjected to the power cycling test," Microelectronics Reliability, vol 51, issues 9-11, pp.1819-1823, 2011
	T. Y. Hung, L. L. Liao, C. C. Wang, W. H. Chi, and K. N. Chiang, "Life Prediction of High Cycle Fatigue in Aluminum Bonding Wires under Power Cycling Test", IEEE Transactions on device and materials reliability, Accepted and to be published

Conference Papers

	H. C. Huang, T. Y. Hung, S. Y. Lin, K. H. Liao, C. C. Wang, K. N. Chiang, "Reliability Assessment of the Temperature Profiles Effect on the Power Module", Published at The 29th National Conference on Theoretical and Applied Mechanics & The 1st International Conference on Mechanics, Nov 8-9, 2013, Hsinchu, Taiwan
	K.C. Lin, C.C. Tsai, Y.F. Su, T.Y. Hung, K.N. Chiang, "Analysis of LED Wire Bonding Process Using Arbitrary Lagrangian-Eulerian and Explicit Time Integration Methods", iMPACT2013, Taipei,Taiwan, Oct 23-25, 2013
	C.J. Huang, T.Y. Hung and K.N. Chiang, "The Mechanical Properties of Carbon Nanotubes Ropes Using Atomistic-Continuum Mechanics and the Equivalent Methods", ICCES 2013, May 24-28, Seattle, USA
	T. Y. Hung, C. C. Wang, and K. N. Chiang, "Bonding Wire Life Prediction Model of the Power Module under Power Cycling Test," EuroSimE 2013, Wroclaw, Poland, April 15-17, 2013.
	C. T. Lai, T. Y. Hung, and K. N. Chiang, "Investigation on the Effect of Surface Roughness on the Fracture Strength of SCS", EuroSimE 2012, Lisbon, Portugal, April 16-18
	H. H. Chang, T. Y. Hung, and K. N. Chiang, "Residual Stress Effect of Electromigration Behavior on Aluminum Strip," Materials for Advanced Metallization Conference, MAM 2012, Grenoble, France, Mar. 11-14, 2012.
	T. Y. Hung, C. J. Huang, C. C. Lee, C. C. Wang, K. C. Lu, and K. N. Chiang, "Thermal Cycling Period Effect of Fatigue Life of the Power Module," Materials for Advanced Metallization Conference, MAM 2012, Grenoble, France, Mar. 11-14, 2012.
	T. Y. Hung, S. Y. Chiang, C. J. Huang, C. C. Wang, K. C. Lu, and K. N. Chiang, "Dwell Time Effect and Thermal Fatigue Life Assessment of Power Module," 13th International Conference on Electronics Materials and Packaging, 3 pp. 2011, Kyoto, Japan
	T. Y. Hung, S. Y. Chiang, C. J. Huang, C. C. Lee, K. N. Chiang, "Thermal-mechanical behavior of the bonding wire for a power module subjected to the power cycling test," 22nd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF), October 3-7, 2011, Bordeaux, France.
	C. Y. Chou, T. Y. Hung, M. C. Yew, W. K. Yang, D. C. Hu, M. C. Tsai, C. S. Huang and K. N. Chiang, "Investigation of stress-buffer-enhanced package subjected to board-level drop test," presented at the Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Micro-Systems, 2008. EuroSimE 2008. International Conference on, 2008.
	C. Y. Chou, T. Y. Hung, M. Sano, S. Y. Yang and K. N. Chiang, "Investigation of Influences of PCB on Board-level Drop Test by Dynamic Simulation and Modal Analysis," in Microsystems, Packaging, Assembly & Circuits Technology Conference, 2008. IMPACT 2008. 3rd International, 2008, pp. 185-188.
	T. Y. Hung, M. C. Yew, C. Y. Chou, K. N. Chiang, and Ieee, "A Study of Thermal Performance for Chip-in-Substrate Package on Package," presented at the 2009 European Microelectronics and Packaging Conference, 2009.
	M. Sano, C. Y. Chou, T. Y. Hung, S. Y. Yang, and K. N. Chiang, "Uncertainty and Reliability Analysis of Chip Scale Package Subjected to Board-level Drop Test," presented at the Eurosime 2009: Thermal, Mechanical and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2009.
	M. Sano, C. Y. Chou, T. Y. Hung, S. Y. Yang, C. J. Huang, K. N. Chiang, and Ieee, "Reliability and Parametric Study on Chip Scale Package Under Board-Level Drop Test," presented at the Impact: 2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference, 2009.
	T. Y. Hung, S. Y. Chiang, C. Y. Chou, C. C. Chiu, and K. N. Chiang, "Thermal design and transient analysis of insulated gate bipolar transistors of power module," presented at the Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2010 12th IEEE Intersociety Conference on, 2010.
	C. Y. Chou, T. Y. Hung, S. Y. Yang, M. C. Yew, W. K. Yang, and K. N. Chiang, "Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact," ESREF2008, 30 Sep. - 03 Oct., Maastricht, Netherland.
	S. Y. Syu, T. Y. Hung, C. J. Huang, H. J. Wang, H. L. Lee and K.N. Chiang, "Reliability Assessment of 3D Chip Stacking Package Using Metal Bonding and Through Silicon Via Technologies," ASME International Mechanical Engineering Congress & Exposition (IMECE), Vancouver, Canada, Nov. 12-18, 2010.
	S. Y. Chiang, T. Y. Hung, Ray Hsing and K. N. Chiang, "Temperature Dependent Current Crowding Analysis of Insulated Gate Bipolar Transistor," ICEP2010, Sapporo, Hokkaido, Japan, May 12-14, 2010.
	C. J. Wu, M. C. Hsieh, C. C. Chiu, T. Y. Hung, M. C. Yew, and K. N. Chiang "Interfacial Delamination Investigation between Copper Bumps in 3D Chip Stacking Package by Using the Modified Virtual Crack Closure Technique," MAM 2010, Mechelen, Belgium, Mar. 7-10, 2010.

參與計畫:

台達電與清華大學合作計畫書: 2009~2013

Master Degree Students

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Chang C. W.

graduated in 2000

Email:

Thesis:

Process Modeling and Reliability Study of ACA/ACF Type Flip Chip Package

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Liu Z. N.

graduated in 2000

Email:

Thesis:

Design and Reliability Analysis of No-Underfill Flip Chip Package

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Lin J. D.

graduated in 2000

Email:

Thesis:

Design and Reliability Analysis of Wafer Level / Flip Chip Package

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Hsu S. M. (Andy)

graduated in 2001

Email: andy-hsu@cmo.com.tw

Thesis:

A study of thermal stress/strain analysis of 3D flip chip package without underfill using Finite Element Method

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Peng C. T.

graduated in 2001

Email: d907710@oz.nthu.edu.tw

Thesis:

Analysis and Validation of Multilayered Structure for Electronic Packaging and MEMs Applications

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Lee C. C.

graduated in 2002

Email: d917716@oz.nthu.edu.tw

Thesis:

Design and Reliability Analysis of Wafer Level Package with Bubble-Like Buffer Layer

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Chen Y. J.

graduated in 2002

Email: starterk89@hotmail.com

Thesis:

Using flip chip solder bump in optical passive alignment

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Liao C. M.

graduated in 2002

Thesis:

Research on Self-Alignment Control of Edge Emitting Laser Diode

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Kuo C. T.

graduated in 2002

Thesis:

Reliability Analysis of Optical Fiber Array Modulus for Transceiver

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Chen C. B. (Louis)

graduated in 2003

Email: chencb@webmail.pme.nthu.edu.tw

Thesis:

Analysis of Reliability and Coupling Efficiency for BGA Type Transceiver

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Sun M. H.

graduated in 2003

Email: mhsun@webmail.pme.nthu.edu.tw

Thesis:

Research of the Microconnectors for the Alignment of Optical Waveguides and Fibers Device

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Chiang H. Y.

graduated in 2004

Email: anne-ch@webmail.pme.nthu.edu.tw

Thesis:

Structural Design and Thermal Analysis of Electro-Thermal Microactuator

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Liu C. C. (Alex)

graduated in 2003

Email: mormor131@webmail.pme.nthu.edu.tw

Thesis:

3D Structure Design and Reliability Analysis of Wafer Level Package with Bubble-like Stress Buffer Layer

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Chang C. H.

graduated in 2004

Email:

Thesis:

Analysis and Design of Nanoscale Strained Silicon

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Liao W. C.

graduated in 2004

Email:

Thesis:

Analysis and Design of the Nano-probe Using Large Deflection Theory

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Chou C. Y. (James)

graduated in 2005

E-mail: chk@webmail.pme.nthu.tw

Thesis:

Investigation of Mechanical Properties of Nano-Scaled Structural Using Atomistic-Continuum Mechanics Method

Homepage: g923770

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Jiang S. N.

graduated in 2006

E-mail: g933777@oz.nthu.edu.tw

Homepage: g933777

Thesis:

Investigation of hysteresis phenomenon of Si-based piezo-resistive pressure sensor.

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Zhu C. H.

graduated in 2006

E-mail: g933761@oz.nthu.edu.tw

Homepage: g933761

Thesis:

Investigation of package effect of Si-based piezo-resistive micro pressure sensor.

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Chien Chung Shih

graduated in 2007

Thesis:

鋁合金輪圈撞擊測試之電腦模擬分析

E-mail: sirius@webmail.pme.nthu.edu.tw

Homepage: g943762

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Jie Shen

graduated in 2007

Thesis:

矽質微型壓阻式壓力感測器之熱遲滯現象研究

E-mail: carb@webmail.pme.nthu.edu.tw

Homepage: g943781

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Wei S. P.

graduated in 2007

Thesis:

具金屬載板之三維堆疊式嵌板型晶圓级封裝其結構可靠度暨熱傳分析

E-mail: shopmanwei@gmail.com

Homepage: g943775

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Huang C.J.

graduated in 2007

Thesis:

奈米尺度下具點缺陷金屬晶體結構之力學性質研究

E-mail: cjh@webmail.pme.nthu.edu.tw

Homepage: g943767

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Deng H.A.

graduated in 2008

Thesis:

Wafer Warpage Analysis of High-power GaN Light Emitting Diode after Laser Lift-off

E-mail:kof2051@yahoo.com.tw

Homepage:g9533562

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Chiang S.Y.

graduated in 2008

Thesis:

Thermal Performance and Embedded Metal Line Reliability Analysis for Quasi-Wafer Level Multi-Chip Module

E-mail:g9533571@oz.nthu.edu.tw

Homepage:g9522571

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Hong D.Y.

graduated in 2008

Thesis:

Reliability Assessment of Chip Size Package under Board-level Drop Test

E-mail:g9533554@oz.nthu.edu.tw

Homepage:g9433554

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Chi W.H.

graduated in 2009

E-mail:g9633558@oz.nthu.edu.tw

Homepage:g9633558

Thesis:

Analysis of Thermal Performance for High Power Light Emitting Diode Lighting Module

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Sano M.

graduated in 2009

E-mail:g9633555@oz.nthu.edu.tw

Homepage:g9633555

Thesis:

Uncertainty and Reliability Analysis of Chip Scale Package Subjected to Board-level Drop Test

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Syu S.Y.

graduated in 2009

E-mail:g9633571@oz.nthu.edu.tw

Homepage:g9633571

Thesis:

Reliability Assessment of 3D Chip Stacking Package Using Metal Bonding and Through Silicon Via Technogies

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Su Y.F.

graduated in 2010

E-mail:g9733550@oz.nthu.edu.tw

Homepage:g9733550

Thesis:

Design of Thermal Performance and Light Degradation Test for High-power Light Emitting Diode

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Wang N.Y.

graduated in 2010

E-mail:g9733559@oz.nthu.edu.tw

Homepage:g9733559

Thesis:

Life Prediction of High Concentration Photovoltaic Module Subjected to Thermal Cycling Test

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Kuo T.H.

graduated in 2010

E-mail:g9733552@oz.nthu.edu.tw

Homepage:g9733552

Thesis:

Reliability Analysis of Through Silicon Via (TSV) Structure and Copper Trace of 3D Chip Stacking Packaging

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Cheng P. C.

E-mail: u940702@oz.nthu.edu.tw

Conference Papers

P. C. Chen, S. Y. Yang, K. N. Chiang "Determination and Verification of Silicon Die Strength Using Ball-Breaker Test," in InterPACK 2011, Jul 6-8, Portland, Oregon, USA, 2011

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Wei S. C.

E-mail: u940771@oz.nthu.edu.tw

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Wang H. J.

E-mail: hahazoon@hotmail.com

Conference Papers

H. J. Wang, H. A.Deng, S. Y. Chiang, and K. N. Chiang "Thin Film Residual Stress Assessment of Capacitive MEMS Microphones Using Process Modeling Technology," in InterPACK 2011, Jul 6-8, Portland, Oregon, USA, 2011

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Lai C. T.

E-mail: u9533213@oz.nthu.edu.tw

Conference Papers

C. T. Lai, T. Y. Hung, and K. N. Chiang, "Investigation on the Effect of Surface Roughness on the Fracture Strength of SCS", EuroSimE 2012, Lisbon, Portugal, April 16-18

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Lee Y. J.

E-mail: u9533115@oz.nthu.edu.tw

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Lin Y. S.

E-mail: soony@yahoo.com.tw

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Fang C. K.

E-mail: kow1139@gmail.com

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Chung Y.

E-mail: u941404@oz.nthu.edu.tw

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Chen H. C.

E-mail: u9633109@oz.nthu.edu.tw

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Lin K. C.

E-mail: b95602006@ntu.edu.tw

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Huang H. J.

E-mail: mindora7871 @hotmail.com

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Yang Y. H.

E-mail: yhy.me96@g2.nctu.edu.tw

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Jiang Y.C

E-mail: jilin1988@hotmail.com

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Tsai C. C.

E-mail: tpg9107tpg@hotmail.com

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Lin S. Y.

E-mail: qqsiyunlin@gmail.com

吳凱強(Kai-Chiang, Wu)

E-mail: kc_wu@tsmc.com

相關著作(Publication)

Conference Papers

K. C. Wu, and K. N. Chiang, “Investigation of solder creep behavior on wafer level CSP under thermal cycling loading,” Electronics Packaging (ICEP), 2014 International Conference on, Toyama, Japan, 23-25 April, 2014.

K. C. Wu, S. Y. Lin and K. N. Chiang, "Investigation of strain rate effect on lifetime performance of wafer level CSP under different thermal cycling loading rate," IMPACT 2014, Taipei, Taiwan, October 22-24, 2014.

K. C. Wu, and K. N. Chiang, " Characterization on Acceleration-Factor Equation for

Packaging-Solder Joint Reliability," Microelectronics Reliability, Accepted and to be published, 2016.

C. H. Lee, K. C. Wu, and K. N. Chiang, "A novel acceleration-factor equation for packaging solder joint," Journal of Mechanics, in press, 2016. (DOI:http

://dx.doi.org/10.1017/jmech.2016.30

)

K. C. Wu, S. Y. Lin, T. Y. Hung, and K. N. Chiang, "Reliability assessment of packaging solder joints under different thermal cycle loading rates," IEEE Transactions on Device and Materials Reliability, vol. 15, pp. 437-442, 2015.

K. C. Wu, C. H. Lee, and K. N. Chiang, “Characterization of thermal cycling ramp rate and dwell time effects on AF (Acceleration Factor) estimation,” ECTC 2016, Las Vegas, USA, May 31- June 3, 2016

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